MU9C3640L-90TZC Ver la hoja de datos (PDF) - Music Semiconductors
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MU9C3640L-90TZC Datasheet PDF : 20 Pages
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LIST-XL
REGISTER BIT ASSIGNMENTS Continued
15 14 13
SDL DCSL
12 11
DCEL
10 9 8
SSL SCSL
76
SCEL
5
LDC
43
DSCV
210
LSC SSCV
Set
Dest.
Seg.
Limits
=0
No
Chng.
=1
Destination
Count
Start
Limit
=00–11
Destination
Count
End
Limit
=00–11
Set
Source
Seg.
Limits
=0
No
Chng.
=1
Source
Count
Start
Limit
=00–11
Source
Count
End
Limit
=00–11
Load
Dest.
Seg.
Count
=0
No
Chng.
=1
Destination
Seg.
Count
Value
=00–11
Load
Src.
Seg.
Count
=0
No
Chng.
=1
Source
Seg.
Count
Value
=00–11
Note: D15, D10, D5, and D2 read back as 0s.
Table 8: Segment Control Register Bit Assignments
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3640L 0
00 0
0
000
Next Free Address, NF7–0
5640L 0
00 0
0
00
Next Free Address, NF8–0
Note: The Next Free Address register is read only, and is accessed by performing a Command
Read cycle immediately following a TCO NF instruction.
Table 9: Next Free Address Register Bit Assignments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
/FL /MM Skip Empty 0
00
0
00 0
0
00 00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3640L 0 0 0
000
0
Match Address, AM7–AM0
/MF
5640L 0
00
0
0
0
Match Address, AM8–AM0
/MF
Note: The Status register is read only, and is accessed by performing Command Read cycles. On
the first cycle, bits 15–0 will be output, and if a second Command Read cycle is issued
immediately after the first Command Read cycle, bits 31–16 will be output.
Table 10: Status Register Bit Assignments
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3640L
Device ID = 341H
PS
5640L
Device ID = 541H
PS
Note: The Persistent Source register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO PS instruction.
Table 11: Persistent Source Register Bit Assignments
Rev. 2
16
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