MU9C3640L-90TZC Ver la hoja de datos (PDF) - Music Semiconductors
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MU9C3640L-90TZC Datasheet PDF : 20 Pages
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LIST-XL
SWITCHING TEST FIGURES
Vc c
R1
T o D evice
Under T est
C1
R2
Figure 4: AC Test Load
Inpu t
W a ve form
0V
5 0 % A m pli tude
P oint
1 0 ns
V IL ( MIN )
Figure 5: Input Signal Waveform
SWITCHING TEST FIGURES COMPONENT VALUES
Component
VCC
R1
R2
C1 (includes jig)
Test Load A
Test Load B
Value
3.3
635
702
30
5
Units
Volts
Ohms
Ohms
pF
pF
SWITCHING CHARACTERISTICS (see note 3)
Cycle Time
-70
-90
No Symbol Parameter (all times in nanoseconds)
Min Max Min Max Notes
1
tELEL Chip Enable Compare Cycle Time
70
90
2
tELEH Chip Enable LOW Pulse Width
Short Cycle: 15
25
4
Medium Cycle: 35
50
4
Long Cycle: 55
75
4
3
tEHEL Chip Enable HIGH Pulse Width
15
15
4
tCVEL Control Input to Chip Enable LOW Set-up Time
2
2
5
5
tELCX Control Input from Chip Enable LOW Hold Time 10
10
5
6
tELQX Chip Enable LOW to Outputs Active
3
3
6
7
tELQV Chip Enable LOW to Outputs Valid
30
50 4,6
8
tEHQZ Chip Enable HIGH to Outputs High-Z
9
tDVEL Data to Chip Enable LOW Set-up Time
10
tELDX Data from Chip Enable LOW Hold Time
11
tELFFV Chip Enable LOW to Full Flag Valid
12 tEHMFX Chip Enable HIGH to /MF, /MM Invalid
13 tEHMFV Chip Enable HIGH to /MF, /MM Valid
14
tRLRH Reset LOW Pulse Width
52
3
10
2
10
50
0
18
100
75 4,6
3
15 7
2
10
75
0
25
100
8
Notes:
1. -1.0V for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (Figure 5).
2. Common I/O lines are clamped, so that signal transients cannot fall below -0.5V.
3. At 0 – 70°C and Vcc(min) to Vcc(max).
4. See Table 6.
5. Control signals are /W and /CM.
6. With load specified in Figure 4, Test Load A.
7. With load specified in Figure 4, Test Load B.
8. /E must be HIGH during this period to ensure accurate default values in the configuration registers.
9. With output and I/O pins unloaded.
Rev. 2
18
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