MU9C3640L-90TZC Ver la hoja de datos (PDF) - Music Semiconductors
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MU9C3640L-90TZC Datasheet PDF : 20 Pages
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INSTRUCTION SET SUMMARY
LIST-XL
MNEMONIC FORMAT
INS dst,src[msk],val
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Instruction: Select Persistent Destination Cont.
Operation
Mnemonic Op-Code
Mem. at Highest-Prio. Match, Emp. SPD M@HM,E
012DH
Masked by MR1
SPD M@HM[MR1],E
016DH
Masked by MR2
SPD M@HM[MR2],E
01ADH
Mem. at Highest-Prio. Match, Skip SPD M@HM,S
Masked by MR1
SPD M@HM[MR1],S
Masked by MR2
SPD M@HM[MR2],S
012EH
016EH
01AEH
Instruction: Select Persistent Source
Operation
Mnemonic
Comparand Register
SPS CR
Mask Register 1
SPS MR1
Mask Register 2
SPS MR2
Memory Array at Addr. Reg. SPS M@[AR]
Memory Array at Address
SPS M@aaaH
Mem. at Highest-Prio. Match SPS M@HM
Op-Code
0000H
0001H
0002H
0004H
0804H
0005H
Instruction: Select Persistent Destination
Operation
Mnemonic Op-Code
Comparand Register
SPD CR
0100H
Masked by MR1
SPD CR[MR1]
0140H
Masked by MR2
SPD CR[MR2]
0180H
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
Masked by MR2
SPD MR1
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V
SPD M@[AR][MR2],V
0108H
0110H
0124H
0164H
01A4H
Mem. at Addr. Reg. set Empty SPD M@[AR],E
Masked by MR1
SPD M@[AR][MR1],E
Masked by MR2
SPD M@[AR][MR2],E
0125H
0165H
01A5H
Mem. at Addr. Reg. set Skip
Masked by MR1
Masked by MR2
SPD M@[AR],S
SPD M@[AR][MR1],S
SPD M@[AR][MR2],S
0126H
0166H
01A6H
Mem. at Addr. Reg. set Random SPD M@[AR],R
Masked by MR1
SPD M@[AR][MR1],R
Masked by MR2
SPD M@[AR][MR2],R
Memory at Address set Valid SPD M@aaaH,V
Masked by MR1
SPD M@aaaH[MR1],V
Masked by MR2
SPD M@aaaH[MR2],V
Memory at Addr. set Empty
Masked by MR1
Masked by MR2
SPD M@aaaH,E
SPD M@aaaH[MR1],E
SPD M@aaaH[MR2],E
Memory at Address set Skip
Masked by MR1
Masked by MR2
SPD M@aaaH,S
SPD M@aaaH[MR1],S
SPD M@aaaH[MR2],S
Mem. at Address set Random SPD M@aaaH,R
Masked by MR1
SPD M@aaaH[MR1],R
Masked by MR2
SPD M@aaaH[MR2],R
0127H
0167H
01A7H
0924H
0964H
09A4H
0925H
0965H
09A5H
0926H
0966H
09A6H
0927H
0967H
09A7H
Mem. at High.-Prio. Match, Random SPD M@HM,R
Masked by MR1
SPD M@HM[MR1],R
Masked by MR2
SPD M@HM[MR2],R
012FH
016FH
01AFH
Mem. at Next Free Addr., Valid SPD M@NF,V
Masked by MR1
SPD M@NF[MR1],V
Masked by MR2
SPD M@NF[MR2],V
0134H
0174H
01B4H
Mem. at Next Free Addr., Empty SPDM@NF,E
Masked by MR1
SPD M@NF[MR1],E
Masked by MR2
SPD M@NF[MR2],E
0135H
0175H
01B5H
Mem. at Next Free Addr., Skip SPD M@NF,S
Masked by MR1
SPD M@NF[MR1],S
Masked by MR2
SPD M@NF[MR2],S
0136H
0176H
01B6H
Mem. at Next Free Addr., Random SPD M@NF,R
Masked by MR1
SPD M@NF[MR1],R
Masked by MR2
SPD M@NF[MR2],R
0137H
0177H
01B7H
Instruction: Temporary Command Override
Operation
Mnemonic
Op-Code
Control Register
TCO CT
0200H
Segment Control Register
TCO SC
0210H
Read Next Free Address
TCO NF
0218H
Address Register
TCO AR
0220H
Read Persistent Source
TCO PS
0230H
Read Persistent Destination TCO PD
0238H
Instruction: Data Move
Operation
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
Masked by MR2
Mnemonic
Op-Code
NOP
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
0300H
0301H
0302H
0304H
0344H
0384H
Memory at Address
Masked by MR1
Masked by MR2
MOV CR,aaaH
MOV CR,aaaH[MR1]
MOV CR,aaaH[MR2]
Mem. at Highest-Prio. Match MOV CR,HM
Masked by MR1
MOV CR,HM[MR1]
Masked by MR2
MOV CR,HM[MR2]
0B04H
0B44H
0B84H
0305H
0345H
0385H
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
Masked by MR1
SPD M@HM[MR1],V
Masked by MR2
SPD M@HM[MR2],V
012CH
016CH
01ACH
13
Rev. 2
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