AS4LC1M16S0 Ver la hoja de datos (PDF) - Alliance Semiconductor
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AS4LC1M16S0 Datasheet PDF : 29 Pages
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AS4LC2M8S1
AS4LC1M16S1
®
CAS
–7
–8
–10
Sym
Parameter
latency Min Max
Min
Max
Min
Max Unit Notes
tMRD
Load mode register to
active/refresh command
2
–
2
–
2
–
tCK
5
3
2
–
2.5
–
3
–
ns
6
Output data hold time @
tOH 30 pF
2
2
–
2.5
–
3
–
ns
6
1
2
–
2.5
–
3
–
ns
6
CKE to CLOCK enable or
tPED power-down exit mode
1
–
1
–
1
–
tCK
Active to precharge
tRAS command
42 120,000 48 120,000 50 120,000 ns
tRC Active command period
70
–
80
–
80
–
ns
8
tRCAR Auto refresh period
70
–
80
–
80
–
ns
tRCD
Active to read or write
delay
3
3
–
3
–
3
–
tCK
8
tREF
Refresh period—2048
rows
–
64
–
64
–
64 ms
Data-out high Z from
3
3
–
3
–
3
–
tCK
9
tROH precharge/burst stop
2
2
–
2
–
2
–
tCK
9
command
1
1
–
1
–
1
–
tCK
9
Precharge command
tRP period
3
3
–
3
–
3
–
tCK
8
Active Bank A to Active
tRRD Bank B command
14
–
16
–
20
–
ns
tT Transition time
tWR WRITE recovery time
Exit SELF REFRESH to
tXSR ACTIVE command
0.3 1.0
0.3
1.0
0.3
1.0 ns
2
–
2
–
2
–
tCK
70
–
80
–
80
–
ns
20
Notes
1 IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
2 Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels.
3 Address transitions average one transition every two-clock period.
4 The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced.
5 tCK = 7 ns for –7, 8 ns for –8, and 10 ns for –10.
6 If clock tr > 1 ns, (tr/2 – 0.5)ns should be added to the parameter.
7 If clock (tr and tf) > 1 ns, [(tr + tf)/2 – 1] ns should be added to the parameter.
8 VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot:
VIL(min) = –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate.
9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter.
10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be
used to reduce the data rate.
11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.
12 Timing actually specified by tWR.
13 tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH
before going to HIGH-Z.
14 CLK must be toggled a minimum of two times during this period.
15 Enables on-chip refresh and address counters.
16 All voltages referenced to VSS.
17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0° C ≤ TA ≤ 70° C) is
endured.
5/21/01; v.1.1
Alliance Semiconductor
P. 9 of 29
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