AS4LC1M16S0 Ver la hoja de datos (PDF) - Alliance Semiconductor

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Fabricante

AS4LC1M16S0

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

®

Command

Pin settings

Description

Burst write

Use the Burst Write command to write data into the SDRAM on

CS = CAS = WE = A10 = low;

RAS = high; A0~A9 = column

address; (A9 = don’t care for

2M × 8; A8, A9 = don’t care

for 1M × 16)

consecutive clock cycles to adjacent column addresses. The burst

length and addressing mode is determined by the mode register

opcode. Input the initial write address in the same clock cycle as the

Burst Write command. Burst terminate behavior for write is the same

as that for read. Terminate the burst with a burst stop command,

precharge command to the same bank or another burst read/write.

DQM can also be used to mask the input data.

Use DQM to mask input and output data. It disables the output buffers

UDQM/LDQM (×16)

DQM (×8) operation

in a read operation and masks input data in a write operation. The

output data is invalid 2 clocks after DQM assertion (2 clock latency).

Input data is masked on the same clock as DQM assertion (0 clock

latency).

Burst stop

CS = WE = low; RAS = CAS = Use burst stop to terminate burst operation. This command may be

high

used to terminate all legal burst lengths.

The Bank Precharge command precharges the bank specified by A11.

Bank precharge

CS = A10 = RAS = WE = low; The precharged bank is switched from active to idle state and is ready

CAS = high; A11 = bank to be activated again. Assert the precharge command after tRAS(min) of

select; A0~A9 = don’t care the bank activate command in the specified bank. The precharge

Precharge all

operation requires a time of tRP(min) to complete.

CS = RAS = WE = low; CAS =

A10 = high; A11, A0~A9 =

don’t care

The Precharge All command precharges both banks simultaneously.

Both banks are switched to the idle state on precharge completion.

Auto precharge

During auto precharge, the SDRAM adjusts internal timing to satisfy

Write: CS = CAS = WE = low ; tRAS(min) and tRP for the programmed CAS latency and burst length.

Couple the auto precharge with a burst read/write operation by

Read: CS = CAS = low;

A10 = high; A11 = bank select;

A0~A9 = column address;

asserting A10 to a high state at the same time the burst read/write

commands are issued. At auto precharge completion, the specified

bank is switched from active to idle state. Note that no new commands

(A9 = don’t care for 2M × 8; A8,

A9 = don’t care for 1M × 16)

(RD/WR/DEAC) can be issued to the same bank until the specified

bank achieves the idle state. Auto precharge does not work with full-

page burst.

When CKE is low, the internal clock is frozen or suspended from the

next clock cycle and the state of the output and burst address are

Clock suspend/power

down mode entry

CKE = low

frozen. If both banks are idle and CKE goes low, the SDRAM enters

power down mode at the next clock cycle. When in power down

mode, no input commands are acknowledged as long as CKE remains

low. To exit power down mode, raise CKE high before the rising edge

of CLK.

Clock suspend/power

down mode exit

CKE = high

Resume internal clock operation by asserting CKE high before the

rising edge of CLK. Subsequent commands can be issued one clock

cycle after the end of the Exit command.

5/21/01; v.1.1

Alliance Semiconductor

P. 11 of 29

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