AS4LC1M16S0 Ver la hoja de datos (PDF) - Alliance Semiconductor

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componentes Descripción

Fabricante

AS4LC1M16S0

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

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(C) WR-P interrupted by RD in another bank

CLK

CMD

WRP (A)

RD (B)

DQ

D(A0)

D(A1)

QB0

QB1

QB2

tRP

Bank A precharge starts

(D) WR-P Interrupted by WR in another bank

CLK

CMD

WRP (A)

WR (B)

Bank A precharge starts

DQ

DA0

DA1

DA2

DB0

DB1

DB2

DB3

AS4LC2M8S1

AS4LC1M16S1

(CL = 2, BL = 4)

QB3

(CL = 3, BL = 4)

Clock suspension read waveforms

CLK external

CLK internal

CKE

DQM

DQ Q1

CLK external

CLK internal

CKE

DQM

DQ Q1

CLK external

CLK internal

CKE

DQM

DQ Q1

Q2

Q3

Q4

Q2

tCKED

Q3

tPED

Q2

Q3

(BL = 8)

OPEN

OPEN

Q6

Q7

Q4

Q6

Q4

Q5

Q6

5/21/01; v.1.1

Alliance Semiconductor

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