AS4LC1M16S0 Ver la hoja de datos (PDF) - Alliance Semiconductor
Número de pieza
componentes Descripción
Fabricante
AS4LC1M16S0 Datasheet PDF : 29 Pages
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AS4LC2M8S1
AS4LC1M16S1
®
read interrupted by write (CL = 2, BL = 4)
CLK
CMD1
DQM1
DQ1
CMD2
DQM2
DQ2
CMD3
DQM3
Read data
Write data
D0
D1
D2
D3
Read data
Write data
Read data
D0
D1
D2
D3
Write data
DQ3
CMD4
DQM4
Read data
DQ4
Q0
To prevent bus contention, maintain a gap between data in and data out.
CLK
tCCD
D0
D1
D2
D3
Write data
D0
D1
D2
D3
read interrupted by write (CL = 3, BL = 4)
CMD1
DQM1
Read data
Write data
DQ1
CMD2
DQM2
DQ2
CMD3
DQM3
D0
D1
D2
D3
Read data
Write data
Read data
D0
D1
D2
D3
Write data
DQ3
CMD4
DQM4
Read data
D0
D1
D2
D3
Write data
DQ4
To prevent bus contention, maintain a gap between data in and data out.
D0
D1
D2
D3
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read
cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle,
burst write data is terminated and the databus goes to High Z simultaneously.
5/21/01; v.1.1
Alliance Semiconductor
P. 20 of 29
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