AS4LC1M16S0 Ver la hoja de datos (PDF) - Alliance Semiconductor

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componentes Descripción

Fabricante

AS4LC1M16S0

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

®

Read—DQM operation*

CLK

T0

tCK*†ƒ T1

tCKS tCKH

tCL T2

tCH

T3

tCL T4

T5

T6

T7

T8

CKE

tCMS tCMH

COMMAND ACTIVE

DQMƒ

A0–A9

A10

BA

tAS tAH

ROW

ROW

tAS tAH

ROW

tAS tAH

BANK

DQ

NOP

READ

tCMS tCMH

NOP

Column m

(A0-A7)3

ENABLE AUTOPRECHARGE

NOP

NOP

NOP

NOP

NOP

tDQZ

DISABLE AUTOPRECHARGE

BANK

tAC*†ƒ

tLZ

tOH

DOUT m

tHZ

tAC*†ƒ

tLZ

tAC*†ƒ

tOH

DOUT m+2

tOH

DOUT m+3

tHZ

tRCD

CAS latency

* For this example, the burst length = 4, and the CAS latency = 2.

† A8 and A9 = “Don’t care.”

ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

Write—DQM operation*

T0

tCK*†ƒ T1

tCL T2

T3

T4

CLK

tCH

tCKS tCKH

CKE

T5

T6

tCMS tCMH

COMMAND ACTIVE

DQMƒ

NOP

WRITE

tCMS tCMH

NOP

NOP

NOP

NOP

A0–A9

tAS tAH

ROW

(CAo0l-uAm7n)†m

A10

BA

tAS tAH

ROW

tAS tAH

BANK

ENABLE AUTOPRECHARGE

DISABLE AUTOPRECHARGE

BANK

DQ

tRCD

tDS tDH

DIN m

tDS tDH

DIN m+2

tDS

tDH

DIN m+3

* For this example, the burst length = 4.

† A8 and A9 = “Don’t care.”

ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

T7

NOP

5/21/01; v.1.1

Alliance Semiconductor

P. 13 of 29

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