BR93A76-WM Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93A76-WM Datasheet PDF : 41 Pages
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BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Description of operations
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and
CS (chip select) for device selection.
When to connect one EEPROM to a microcontroller, connect it as shown in Fig.59(a) or Fig.59(b). When to use the input and
output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.59(b) (Refer to pages
17/35.), and connection by 3 lines is available.
In the case of plural connections, refer to Fig. 59 (c).
Micro-
controller
CS
SK
DO
BR93LXX
/AXX
CS
SK
DI
Micro-
controller
CS
SK
DO
BR93LXX
/AXX
CS
SK
DI
Micro-
controller
CS3
CS1
CS0
SK
DO
DI
DI
DO
DO
Device 1
Device 2
Device 3
Fig.59-(a) Connection by 4 lines
Fig.59-(b) Connection by 3 lines
Fig.59-(c) Connection example of plural devices
Fig.59 Connection method with microcontroller
Communications of the Microwire Bus are started by the first “1” input after the rise of CS. This input is called a start bit. After
input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners.
“0” input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the
microcontroller, input “0” before the start bit input, to control the bit width.
●Command mode
Command
Start
bit
Ope
code
BR93L46-W
BR93A46-WM
Address
BR93L56/66-W
BR93A56/66-WM
BR93L76/86-W
BR93A76/86-WM
Data
Read (READ)
*1
1
10
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 D15~D0(READ DATA)
Write enable (WEN)
1
00
1 1 ****
1 1 ******
1 1 ********
Write (WRITE)
*2
1
01
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 D15~D0(WRITE DATA)
Write all (WRAL)
*2
1
00
0 1 ****
0 1 ******
0 1 ********
D15~D0(WRITE DATA)
Write disable (WDS)
1
00
0 0 ****
0 0 ******
0 0 ********
Erase (ERASE)
1
11
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
Chip erase (ERAL)
1
00
1 0 ****
1 0 ******
1 0 ********
・ Input the address and the data in MSB first manners.
・ As for *, input either VIH or VIL.
*Start bit
A7 of BR93L56-W/A56-WM becomes Don't Care.
A9 of BR93L76-W/A76-WM becomes Don't Care.
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit means the first “1” input after the rise of CS.
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and
address data in significant order are sequentially output continuously. (Auto increment function)
*2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
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2011.02 - Rev.F
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