BR93A76-WM Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93A76-WM Datasheet PDF : 41 Pages
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BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Application
1) Method to cancel each command
○READ
Start bit
Ope code
Address *1
1bit
2bit
6bit
Cancel is available in all areas in read mode.
・Method to cancel：cancel by CS=“L”
Fig.66 READ cancel available timing
Data
16bit
(In the case of BR93L46-W/A46-WM)
＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
○WRITE, WRAL
・25 Rise of clock *2
SK
24 25
DI D1 D0
Enlarged figure
Start bit
1bit
Ope code
2bit
Address *1
6bit
a
Data
16bit
a：From start bit to 25 clock rise＊2
Cancel by CS=“L”
b：25 clock rise and after＊2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
tE/W
(In the case of BR93L46-W/A46-WM)
b
*1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM
*2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
Start bit
1bit
29 Rise of clock *2
SK
28 29 30 31
DI D1
D0
a
b
c
Enlarged figure
Ope code
2bit
Address *1
10bit
a
Data
16bit
b
tE/W
c
(In the case of BR93L86-W/A86-WM)
a：From start bit to 29 clock rise
Cancel by CS=“L”
b：29 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：30 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Note 1) If Vcc is made OFF in this area, designated address data is
not guaranteed, therefore write once again.
Note 2) If CS is started at the same timing as that of the SK rise,
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.67 WRITE, WRAL cancel available timing
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14/40
2011.02 - Rev.F
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