BR93A76-WM Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93A76-WM Datasheet PDF : 41 Pages
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BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
4) Write enable (WEN) / disable (WDS) cycle
～～
CS
SK
DI
DO
High-Z
1
2
34
1
00
5
67
8 ～～ n
ENABLE=1 1
DISABLE=0 0 ～ ～
～～
BR93L46-Ｗ/A46-WM : n=9
BR93L56-W/A56-WM
BR93L66-W/A66-WM
: n=11
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=13
Fig.63 Write enable (WEN) / disable (WDS) cycle
○ At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable / diable
command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○ When the write enable command is executed after power on, write enable status gets in. When the write disable command
is executed then, the IC gets in write disable status as same as at power on, and then the write command is canceled
thereafter in software manner. However, the read command is executable. In write enable status, even when the write
command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable
command after completion of write.
5) Erase cycle timing (ERASE)
CS
SK
DI
DO
High-Z
～～
～～
tCS
STATUS
～～
～～
～～
～～
12
4
～～
n
～～
～～
111
Am
～ ～ A3 A2 A1 A0
～～
～～
～～
tSV
～～
BU～ ～SY READY
tE/W
Fig.64 Erase cycle timing
BR93L46-W/A46-WM : n=9, m=5
BR93L56-W/A56-WM
BR93L66-W/A66-WM
: n=11, m=7
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=13, m=9
○In this command, data of the designated address is made into “1”. The data of the designated address becomes “FFFFh”.
Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
6) Chip erase cycle timing (ERAL)
CS
SK
12
4
～～
tCS
～～ n
～～
STATUS
～～
～～
～～
～～
～～
DI
DO
High-Z
1 00
1
0
Fig.65 Chip erase cycle timing
～～
～～
tSV
～～
BUS～ ～ Y READY
tE/W
BR93L46-W/A46-WM : n=9
BR93L56-W/A56-WM
BR93L66-W/A66-WM
: n=11
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=13
○In this command, data of all addresses is erased. Data of all addresses becomes ”FFFFh”.
Actual ERASE starts at the fall of CS after the falll of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
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2011.02 - Rev.F
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