BR93A76-WM Ver la hoja de datos (PDF) - ROHM Semiconductor

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BR93A76-WM

High Reliability Series EEPROMs Microwire BUS

ROHM Semiconductor 

BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series

Technical Note

○ERASE, ERAL

Start bit

1bit

Ope code

2bit

Address *1

6bit

a

9 Rise of clock＊2

SK

89

DI

1/2

tE/W

A1

A0

Enlarged figure

(In the case of BR93L46-W/A46-WM)

b

a：From start bit to 9 clock rise＊2

Cancel by CS=“L”

b：9 clock rise and after＊2

Cancellation is not available by any means. If Vcc is made OFF in this area,

designated address data is not guaranteed, therefore write once again.

And when SK clock is input continuously, cancellation is not available.

＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM

Address is 10 bits in BR93L76-W/A76-WM

＊2 11 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM

13 clocks in BR93L76-W/A76-WM

Start bit

1bit

Ope code

2bit

a

Address *1

10bit

b

13 Rise of clock *2

SK

12 13 14 15

DI D1

a

b

c

Enlarged figure

tE/W

(In the case of BR93L86-W/A86-WM)

c

a：From start bit to 13 clock rise

Cancel by CS=“L”

b：13 clock rise and after

Cancellation is not available by any means. If Vcc is made OFF in this area,

designated address data is not guaranteed, therefore write once again.

c：14 clock rise and after

Cancel by CS=“L”

However, when write is started in b area (CS is ended), cancellation is not

available by any means.

And when SK clock is output continuously is not available.

Note 1) If Vcc is made OFF in this area, designated address data is

not guaranteed, therefore write once again.

Note 2) If CS is started at the same timing as that of the SK rise,

write execution/cancel becomes unstable, therefore, it is

recommended to fail in SK=”L” area.

As for SK rise, recommend timing of tCSS/tCSH or higher.

Fig.68 ERASE, ERAL cancel available timing

2) At standby

○Standby current

When CS is “L”, SK input is “L”, DI input is “H”, and even with middle electric potential, current does not increase.

○Timing

As shown in Fig.69, when SK at standby is “H”, if CS is started, DI status may be read at the rise edge.

At standby and at power ON/OFF, when to start CS, set SK input or DI input to “L” status. (Refer to Fig.70)

CS=SK=DI=”H”

Wrong recognition as a start bit

If CS is started when SK=”L” or DI=”L”, a start

bit is recognized correctly.

CS

Start bit input

SK

DI

CS

Start bit input

SK

DI

Fig.69 Wrong action timing

Fig.70 Normal action timing

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2011.02 - Rev.F

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