SSD0858Z Ver la hoja de datos (PDF) - Solomon Systech

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SSD0858Z

LCD Segment / Common Driver with Controller

Solomon Systech  

b. The D/C bit determines the next data byte is acted as a command or a data. If the D/C bit is

set to logic “0”, it defines the following data byte as a command. If the D/C bit is set to logic

“1”, it defines the following data byte as a data which will be stored at the GDDRAM. The

GDDRAM column address pointer will be increased by one automatically after each data

write.

6) Acknowledge bit will be generated after receiving each control byte or data byte.

7) The write mode will be finished when a stop condition is applied. The stop condition is also defined

in Figure 9. The stop condition is established by pulling the “SDA in” from low to high while the “SCL”

stays high.

TDH, START

TDS, STOP

SDA

SDA

SCL

S

START condition

SCL

P

STOP condition

Figure 9 - Definition of the start and stop condition

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

1

2

S

START

Condition

Non-acknowledge

Acknowledge

8

9

Clock pulse for

acknowledgement

Figure 10 - Definition of the acknowledgement condition

Please be noted that the transmission of the data bit has some limitations.

1. The data bit, which is transmitted during each SCL pulse, must be kept at a stable state within the

“high” period of the clock pulse. Please refer to the Figure 11 for graphical representations. Except in

start or stop conditions, the data line can be switched only when the SCL is low.

2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.

23

SSD0858

Rev 1.0

11/2002

SOLOMON

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