TE28F400B3T110 Ver la hoja de datos (PDF) - Intel
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TE28F400B3T110 Datasheet PDF : 48 Pages
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SMART 3 ADVANCED BOOT BLOCK
Table 7. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS) Check Write State Machine bit first to determine
1 = Ready
word program or block erase completion, before
0 = Busy
checking program or erase status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When erase suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to “1.”
ESS bit remains set at “1” until an Erase Resume
command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max. number of erase pulses to the block and is still
unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted but
failed to program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous
indication of VPP level. The WSM interrogates VPP
level only after the Program or Erase command
sequences have been entered, and informs the
system if VPP has not been switched on. The VPP is
also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report
accurate feedback between VPPLK max and VPP1 min
or between VPP1 max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to “1.”
PSS bit remains set to “1” until a Program Resume
command is issued.
SR.1 = Block Lock Status
1 = Program/Erase attempted on locked
block; Operation aborted
0 = No operation to locked blocks
If a program or erase operation is attempted to one
of the locked blocks, this bit is set by the WSM. The
operation specified is aborted and the device is
returned to read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
This bit is reserved for future use and should be
masked out when polling the status register.
PRELIMINARY
19
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