TE28F400B3T110 Ver la hoja de datos (PDF) - Intel

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TE28F400B3T110

SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY

Intel 

SMART 3 ADVANCED BOOT BLOCK

E

Table 6. Command Bus Definitions(1, 4)

First Bus Cycle

Second Bus Cycle

Command

Notes Oper Addr

Data

Oper

Addr

Data

Read Array

Write

X

FFH

Read Identifier

2

Write

X

90H

Read

IA

ID

Read Status Register

Write

X

70H

Read

X

SRD

Clear Status Register

Write

X

50H

Program

3

Write

X 40H / 10H Write

PA

PD

Block Erase/Confirm

Write

X

20H

Write

BA

D0H

Program/Erase Suspend

Write

X

B0H

Program/Erase Resume

Write

X

D0H

NOTES: PA: Program Address

PD: Program Data BA: Block Address

IA: Identifier Address

ID: Identifier Data SRD: Status Register Data

1. Bus operations are defined in Table 3.

2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. A0 = 0 for

manufacturer code, A0 = 1 for device code. A1—A21 = 0.

3. Either 40H or 10H command is valid although the standard is 40H.

4. When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH, to minimize current

draw.

18

PRELIMINARY

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