5962R9582101QXC Ver la hoja de datos (PDF) - Intersil
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5962R9582101QXC Datasheet PDF : 21 Pages
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HS-82C37ARH
CHANNEL
REGISTER
SIGNALS
OPERATION CS IOR IOW A3 A2 A1 A0
INTERNAL
FLIP-FLOP
0
Base and Current
Address
Write
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
Current Address
Read
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
Base and Current Word
Write
0
1
0
0
0
0
1
0
Count
0
1
0
0
0
0
1
1
Current Word Count
Read
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
Base and Current
Address
Write
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
Current Address
Read
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
Base and Current Word
Write
0
1
0
0
0
1
1
0
Count
0
1
0
0
0
1
1
1
Current Word Count
Read
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
2
Base and Current
Address
Write
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
Current Address
Read
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
Base and Current Word
Write
0
1
0
0
1
0
1
0
Count
0
1
0
0
1
0
1
1
Current Word Count
Read
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
3
Base and Current
Address
Write
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
Current Address
Read
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
Base and Current Word
Write
0
1
0
0
1
1
1
0
Count
0
1
0
0
1
1
1
1
Current Word Count
Read
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
FIGURE 11. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
DATA BUS
DB0-DB7
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
Application Information
Figure 12 shows an application for a DMA system utilizing
the HS-82C37ARH DMA controller and the HS-80C86RH
Microprocessor. In this application, the HS-82C37ARH DMA
controller is used to improve system performance by
allowing an I/O device to transfer data directly to or from
system memory.
Components
The system clock is generated by the HS-82C85RH clock
controllers generator and is inverted to meet the clock high
and low times required by the HS-82C37ARH DMA
controller. The four OR gates are used to support the
HS-80C86RH Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The
HS-82C37ARH multiplexes the most significant bits of the
address on its data outputs (DB0 - 7), so the 82C82 octal
latch is used to demultiplex the address. A three-state
inverter is used to generate the BHE signal using the A0
output of the HS-82C37ARH. Hold Acknowledge (HLDA)
and Address Enable (AEN) are “ORed” together and used to
deactivate the microprocessors 82C82 transceiver to insure
that the DMA controller does not have bus contention with
the microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold Request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold
Acknowledge (HLDA) signal is returned to the DMA
controller from the HS-80C86RH processor. After the Hold
Acknowledge has been received, addresses and control
signals are generated by the DMA controller to accomplish
the DMA transfers. Data is transferred directly from the I/O
device to memory (or vice versa) with IOR and MEMW (or
MEMR and IOW) being active. Note that data is not read into
or driven out of the DMA controller in I/O-to-Memory or
Memory-to-I/O data transfers.
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