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5962R9582101QXC Datasheet PDF : 21 Pages
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HS-82C37ARH
NAME
SIZE
NUMBER
Base Address Registers
16 bits
4
Base Word Count Registers
16 bits
4
Current Address Registers
16 bits
4
Current Word Count Registers
16 bits
4
Temporary Address Register
16 bits
1
Temporary Word Count Register
16 bits
1
Status Register
8 bits
1
Command Register
8 bits
1
Temporary Register
8 bits
1
Mode Registers
6 bits
4
Mask Registers
4 bits
1
Request Register
4 bits
1
FIGURE 8. HS-82C37ARH INTERNAL REGISTERS
DMA Operation
In a system, the HS-82C37ARH address and control outputs
and data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the
HS-82C37ARH drives the busses and generates the control
signals to perform the data transfer. The operation
performed by activating one of the four DMA request inputs
has previously been programmed into the controller via the
Command, Mode, Address, and Word Count Registers.
For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the HS-82C37ARH Current and Base Address
Registers for a particular channel, and the length of the block
is loaded into that channel’s Word Count Register. The
corresponding Mode Register is programmed for a
Memory-to-I/O operation (read transfer), and various options
are selected by the Command Register and other Mode
Register bits. The channel’s mask bit is cleared to enable
recognition of a DMA request (DREQ). The DREQ can either
be a hardware signal or a software command.
Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count Register
underflows, or an external EOP is applied.
To further understand HS-82C37ARH operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, Active and Idle.
After being programmed, the controller is normally Idle until
a DMA request occurs on an unmasked channel, or a
software request is given. The HS-82C37ARH will then
request control of the system busses and enter the Active
cycle. The Active cycle is composed of several internal
states, depending on what options have been selected and
what type of operation has been requested.
The HS-82C37ARH can assume seven separate states,
each composed of one full clock period. State I (SI) is the
Idle state. It is entered when the HS-82C37ARH has no valid
DMA requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program
Condition (being programmed by the processor.)
State 0 (S0) is the first state of a DMA service. The
HS-82C37ARH has requested a hold but the processor has
not yet returned an acknowledge. The HS-82C37ARH may
still be programmed until it has received HLDA from the
CPU. An acknowledge from the CPU will signal that DMA
transfers may begin. S1, S2, S3 and S4 are the working
states of the DMA service. If more time is needed to
complete a transfer than is available with normal timing, wait
states (SW) can be inserted between S2 or S3 and S4 by
the use of the Ready line on the HS-82C37ARH.
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the HS-82C37ARH in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-Memory transfers require a read-from and a
write-to-memory to complete each transfer. The states,
which resemble the normal working states, use two-digit
numbers for identification. Eight states are required for a
single transfer. The first four states (S11, S12, S13, S14) are
used for the read-from-memory half and the last four states
(S21, S22, S23, S24) for the write-to-memory half of the
transfer.
Idle Cycle
When no channel is requesting service, the HS-82C37ARH
will enter the Idle cycle and perform “SI” states. In this cycle,
the HS-82C37ARH will sample the DREQ lines on the falling
edge of every clock cycle to determine if any channel is
requesting a DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
HS-82C37ARH. When CS is low and HLDA is low, the
HS-82C37ARH enters the Program Condition. The CPU can
now establish, change or inspect the internal definition of the
part by reading from or writing to the internal registers.
12
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