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5962R9582101QXC

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil 

HS-82C37ARH

the microprocessor in the Program Condition. Following the

end of a DMA service it may also be reinitialized by an

Autoinitialization back to its original value. Autoinitialization

can occur only when an EOP occurs. If it is not

Autoinitialized, this register will have a count of FFFFH after

TC.

Base Address and Base Word Count Registers - Each

channel has a pair of Base Address and Base Word Count

Registers. These 16-bit registers store the original value of

their associated current registers. During Autoinitialization,

these values are used to restore the current registers to their

original values. The base registers are written

simultaneously with their corresponding current register in

8-bit bytes in the Program Condition by the microprocessor.

These registers cannot be read by the microprocessor.

Mask Register - Each channel has associated with it a

mask bit which can be set to disable an incoming DREQ.

Each mask bit is set when its associated channel produces

an EOP if the channel is not programmed to Autoinitialize.

Each bit of the 4-bit Mask Register may also be set or

cleared separately or simultaneously under soft-ware

control. The entire register is also set by a Reset or Master

Clear. This disables all hardware DMA requests until a clear

Mask Register instruction allows them to occur. The

instruction to separately set or clear the mask bits is similar

in form to that used with the Request Register. Refer to the

following table and Figure 10 for details. When reading the

Mask Register, bits 4-7 will always read as logical ones, and

bits 0-3 will display the mask bits of channel 0-3,

respectively. The 4 bits of the Mask Register may be cleared

simultaneously by using the Clear Mask Register command

(see software commands section).

Mask Register

76543210

BIT NUMBER

DON’T CARE

00 SELECT CHANNEL 0 MASK BIT

01 SELECT CHANNEL 1 MASK BIT

10 SELECT CHANNEL 2 MASK BIT

11 SELECT CHANNEL 3 MASK BIT

0 CLEAR MASK BIT

1 SET MASK BIT

All four bits of the Mask Register may also be written with a

single command.

76543210

DON’T CARE,

WRITE ALL

ONES,

READ

BIT NUMBER

0 CLEAR CHANNEL 0 MASK BIT

1 SET CHANNEL 0 MASK BIT

0 CLEAR CHANNEL 1 MASK BIT

1 SET CHANNEL 1 MASK BIT

0 CLEAR CHANNEL 2 MASK BIT

1 SET CHANNEL 2 MASK BIT

0 CLEAR CHANNEL 3 MASK BIT

1 SET CHANNEL 3 MASK BIT

Mode Register - Each channel has a 6-bit Mode Register

associated with it. When the register is being written to by

the microprocessor in the Program Condition, bits 0 and 1

determine which channel Mode Register is to be written.

When the processor reads a Mode Register, bits 0 and 1 will

both be ones. See the adjacent table and Figure 10 for Mode

Register functions and addresses.

Mode Register

76543210

BIT NUMBER

00 CHANNEL 0 SELECT

01 CHANNEL 1 SELECTT

10 CHANNEL 2 SELECT

11 CHANNEL 3 SELECT

XX READBACK

00 VERIFY TRANSFER

01 WRITE TRANSFER

10 READ TRANSFER

11 ILLEGAL

XX IF BITS 6 AND 7 = 11

0 AUTOINITIALIZATION DISABLE

1 AUTOINITIALIZATION ENABLE

0 ADDRESS INCREMENT SELECT

1 ADDRESS DECREMENT SELECT

00 DEMAND MODE SELECT

01 SINGLE MODE SELECT

10 BLOCK MODE SELECT

11 CASCADE MODE SELECT

Request Register - The HS-82C37ARH can respond to

requests for DMA service which are initiated by software as

well as by a DREQ. Each channel has a request bit

associated with it in the 4-bit Request Register. These are

non-maskable and subject to prioritization by the Priority

Encoder network. Each register bit is set or reset separately

under software control. The entire register is cleared by a

Reset. To set or reset a bit, the software loads the proper

form of the data word. See Figure 10 for register address

coding, and the following table for Request Register format.

A software request for DMA operation can be made in Block

or Single Modes. For Memory-to-Memory transfers, the

software request for channel 0 should be set. When reading

the Request Register, bits 4-7 will always read as ones, and

bits 0-3 will display the request bits of channels 0-3

respectively.

Request Register

76543210

DON’T CARE,

WRITE BITS 4-7

ALL ONES, READ

BIT NUMBER

00 SELECT CHANNEL 0

01 SELECT CHANNEL 1

10 SELECT CHANNEL 2

11 SELECT CHANNEL 3

0 RESET REQUEST BIT

1 SET REQUEST BIT

Command Register - This 8-bit register controls the

operation of the HS-82C37ARH. It is programmed by the

microprocessor and is cleared by Reset or a Master Clear

16

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