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5962R9582101QXC

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil 

HS-82C37ARH

Software Commands

There are special software commands which can be

executed by reading or writing to the HS-82C37ARH. These

commands do not depend on the specific data pattern on the

data bus, but are activated by the I/O operation itself. On

read type commands, the data value is not guaranteed.

These commands are:

Clear First/Last Flip-Flop: This command is executed prior

to writing or reading new address or word count information

to the HS-82C37ARH. This initializes the flip-flop to a known

state so that subsequent accesses to register contents by

the microprocessor will address upper and lower bytes in the

correct sequence.

Set First/Last Flip-Flop: This command will set the flip-flop

to select the high byte first on read and write operations to

Address and Word Count registers.

Master Clear: This software instruction has the same effect

as the hardware Reset. The Command, Status, Request,

and Temporary Registers, and Internal First/Last Flip-Flop

and Mode Register Counter are cleared and the Mask

Register is set. The HS-82C37ARH will enter the Idle cycle.

Clear Mask Register: This command clears the mask bits

of all four channels, enabling them to accept DMA requests.

Clear Mode Register Counter: Since only one address

location is available for reading the Mode Registers, an

internal two-bit counter has been included to select Mode

Registers during read operations. To read the Mode

Registers, first execute the Clear Mode Register Counter

command, then do consecutive reads until the desired

channel is read. Read order is channel 0 first, channel 3 last.

The lower two bits on all Mode Registers will read as ones.

External EOP Operation

The EOP pin is a bidirectional, open drain pin which may be

driven by external signals to terminate DMA operation.

Because EOP is an open drain pin an external pull-up resistor

is required. The value of the external pull-up resistor used

should guarantee a rise time of less than 125ns. It is important

to note that the HS-82C37ARH will not accept external EOP

signals when it is in an SI (Idle)state. The controller must be

active to latch EXT EOP. Once latched, the EXT EOP will be

acted upon during the next S2 state, unless the HS-

82C37ARH enters an Idle state first. In the latter case the

latched EOP is cleared. External EOP pulses occurring

between active DMA transfers in demand mode will not be

recognized, since the HS-82C37ARH is in an SI state.

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