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5962R9582101QXC Datasheet PDF : 21 Pages
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HS-82C37ARH
2ND LEVEL
HS-80C86RH
MICRO-
PROCESSOR
1ST LEVEL
HRQ DREQ
HLDA DACK
HS-82C37ARH
DREQ
DACK
INITIAL DEVICE
HS-82C37ARH
HRQ
HLDA
HRQ
HLDA
HS-82C37ARH
ADDITIONAL
DEVICES
FIGURE 9. CASCADED HS-82C37ARHs
When programming cascaded controllers, start with the first
level (closest to the microprocessor). After RESET, the
DACK outputs are programmed to be active low and are held
in the high state. If they are used to drive HLDA directly, the
second level device(s) cannot be programmed until DACK
polarity is selected as active high on the initial device. Also,
the initial device’s mask bits function normally on cascaded
channels, so they may be used to inhibit second-level services.
Transfer Types
Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory
by activating MEMW and IOR. Read transfers move data from
memory to an I/O device by activating MEMR and IOW.
Verify transfers are pseudo-transfers. The HS-82C37ARH
operates as in Read or Write transfers generating addresses
and responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted
for Memory-to-Memory operation. Ready is ignored during
Verify transfers.
Autoinitialize - By programming a bit in the Mode Register,
a channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count Registers are automatically
restored from the Base Address and Base Word Count
Registers of that channel following EOP. The base registers
are loaded simultaneously with the current registers by the
microprocessor and remain unchanged throughout the DMA
service. The mask bit is not set when the channel is in
Autoinitialize. Following Autoinitialization, the channel is
ready to perform another DMA service, without CPU
intervention, as soon as a valid DREQ is detected, or software
request made.
Memory-to-Memory - To perform block moves of data from
one memory address space to another with minimum of
program effort and time, the HS-82C37ARH includes a
Memory-to-Memory transfer feature. Programming a bit in
the Command Register selects channels 0 and 1 to operate
as Memory-to-Memory transfer channels.
The transfer is initiated by setting the software or hardware
DREQ for channel 0. The HS-82C37ARH requests a DMA
service in the normal manner. After HLDA is true, the device,
using four-state transfers in Block Transfer Mode, reads data
from the memory. The channel 0 Current Address Register is
the source for the address used and is decremented or
incremented in the normal manner. The data byte read from the
memory is stored in the HS-82C37ARH internal Temporary
Register. Another four-state transfer moves the data to memory
using the address in channel 1’s Current Address Register and
incrementing or decrementing it in the normal manner. The
channel 1 Current Word Count Register is decremented.
When the word count of channel 1 goes to FFFFH, a TC is
generated causing an EOP output terminating the service.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the Status Register or generate an
EOP in this mode. It will cause an Autoinitialization of
channel 0, if that option has been selected.
If full Autoinitialization for a Memory-to-Memory operation is
desired, the channel 0 and channel 1 word counts must be
set equal before the transfer begins. Otherwise, if channel 0
underflows before channel 1, it will Autoinitialize and set the
data source address back to the beginning of the block. If the
channel 1 word count underflows before channel 0, the
Memory-to-Memory DMA service will terminate, and
channel 1 will Autoinitialize but channel 0 will not.
In Memory-to-Memory Mode, Channel 0 may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by bit 1 in
the Command Register.
The HS-82C37ARH will respond to external EOP signals
during Memory-to-Memory transfers, but will only relinquish
the system busses after the transfer is complete (i.e., after
an S24 state). Data comparators in block search schemes
may use this input to terminate the service when a match is
found. The timing of Memory-to-Memory transfers is found in
Figure 5. Memory-to-Memory operations can be detected as
an active AEN with no DACK outputs.
Priority - The HS-82C37ARH has two types of priority
encoding available as software selectable options. The first
is Fixed Priority which fixes the channels in priority order
based upon the descending value of their numbers. The
channel with the lowest priority is 3 followed by 2, 1 and the
highest priority channel, 0. After the recognition of any one
channel for service, the other channels are prevented from
interfering with the service until it is completed.
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