ICL7109 Ver la hoja de datos (PDF) - Intersil
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ICL7109 Datasheet PDF : 25 Pages
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ICL7109
INTEGRATOR
OUTPUT
INTERNAL
CLOCK
DEINT TERMINATED
AT ZERO CROSSING
DETECTION
AUTOZERO
PHASE I
MIN 1790 COUNTS
MAX 2041 COUNTS
STATIC IN
HOLD STATE
7 COUNTS
INT
PHASE II
INTERNAL
LATCH
STATUS
OUTPUT
RUN/HOLD
INPUT
FIGURE 5. RUN/HOLD OPERATION
If RUN/HOLD goes low at any time during Deintegrate (Phase
III) after the zero crossing has occurred, the circuit will imme-
diately terminate Deintegrate and jump to Auto-Zero. This fea-
ture can be used to eliminate the time spent in Deintegrate
after the zero-crossing. If RUN/HOLD stays or goes low, the
converter will ensure minimum Auto-Zero time, and then wait
in Auto-Zero until the RUN/HOLD input goes high. The con-
verter will begin the Integrate (Phase II) portion of the next
conversion (and the STATUS output will go high) seven clock
periods after the high level is detected at RUN/HOLD. See
Figure 5 for details.
Using the RUN/HOLD input in this manner allows an easy
“convert on demand” interface to be used. The converter may
be held at idle in auto-zero with RUN/HOLD low. When
RUN/HOLD goes high the conversion is started, and when
the STATUS output goes low the new data is valid (or trans-
ferred to the UART; see Handshake Mode). RUN/HOLD may
now be taken low which terminates deintegrate and ensures a
minimum Auto-Zero time before the next conversion.
Alternately, RUN/HOLD can be used to minimize conversion
time by ensuring that it goes low during Deintegrate, after zero
crossing, and goes high after the hold point is reached. The
required activity on the RUN/HOLD input can be provided by
connecting it to the Buffered Oscillator Output. In this mode
the conversion time is dependent on the input value
measured. Also refer to Intersil Application Note AN032 for a
discussion of the effects this will have on Auto-Zero
performance.
If the RUN/HOLD input goes low and stays low during Auto-
Zero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for RUN/HOLD to go high. As above, Inte-
grate (Phase II) begins seven clock periods after the high
level is detected.
Direct Mode
When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity and
over-range high order byte) are accessible under control of
the byte and chip enable terminals as inputs. These three
inputs are all active low, and are provided with pullup resistors
to ensure an inactive high level when left open. When the chip
enable input is low, taking a byte enable input low will allow
the outputs of that byte to become active (three-stated on).
This allows a variety of parallel data accessing techniques to
be used, as shown in the section entitled “Interfacing.” The
timing requirements for these outputs are shown in Figure 6
and Table 1.
It should be noted that these control inputs are
asynchronous with respect to the converter clock - the data
may be accessed at any time. Thus it is possible to access
the latches while they are being updated, which could lead to
erroneous data. Synchronizing the access of the latches with
the conversion cycle by monitoring the STATUS output will
prevent this. Data is never updated while STATUS is low.
TABLE 1. DIRECT MODE TIMING REQUIREMENTS
(See Note 4 of Electrical Specifications)
DESCRIPTION SYMBOL MIN TYP MAX UNITS
Byte Enable
Width
tBEA
350 220
-
ns
Data Access
Time from Byte
Enable
tDAB
- 210 350
ns
Data Hold Time
from Byte
Enable
tDHB
- 150 300
ns
Chip Enable
Width
tCEA
400 260
-
ns
Data Access
Time from Chip
Enable
tDAC
- 260 400
ns
Data Hold Time
from Chip
Enable
tDHC
- 240 400
ns
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