ICL7109 Ver la hoja de datos (PDF) - Intersil
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ICL7109 Datasheet PDF : 25 Pages
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ICL7109
converter. When the MODE pin is low or left open (this input
is provided with a pulldown resistor to ensure a low level
when the pin is left open), the converter is in its “Direct” out-
put mode, where the output data is directly accessible under
the control of the chip and byte enable inputs. When the
MODE input is pulsed high, the converter enters the UART
handshake mode and outputs the data in two bytes, then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Signal Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 3 for of this tim-
ing. This signal may be used as a “data valid” flag (data never
changes while STATUS is low) to drive interrupts, or for
monitoring the status of the converter.
RUN/HOLD Input
When the RUN/HOLD input is high, or left open, the circuit will
continuously perform conversion cycles, updating the output
latches after zero crossing during the Deintegrate (Phase III)
portion of the conversion cycle (See Figure 3). In this mode of
operation, the conversion cycle will be performed in 8192
clock periods, regardless of the resulting value.
TEST
17
HIGH ORDER
BYTE OUTPUTS
LOW ORDER
BYTE OUTPUTS
BB BBB B BBBBB B
POL OR 12 11 10 9 8 7 6 5 4 3 2 1
3 4 5 6 7 8 9 10 11 12 13 14 15 16
14 THREE-STATE OUTPUTS
18
19
20
LBEN
HBEN
CE/LOAD
14 LATCHES
TO
ANALOG
SECTION
COMP OUT
AZ
INT
DEINT (+)
DEINT (-)
12-BIT COUNTER
LATCH
CLOCK
CONVERSION
CONTROL LOGIC
OSCILLATOR
AND CLOCK
CIRCUITRY
HANDSHAKE
LOGIC
2
STATUS
26
22 23 24 25
21
RUN/ OSC OSC OSC BUF MODE
HOLD IN OUT SEL OSC
OUT
FIGURE 4. DIGITAL SECTION
27
SEND
1
GND
12
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