MU9C3480L-12DC Ver la hoja de datos (PDF) - Music Semiconductors

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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

OPERATIONAL CHARACTERISTICS (CONT’D)

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Set Destination

Dest. Count

Seg.

Start

Limits Limit

= “0” “00 - 11”

No

Chng.

= “1”

Destination Set

Count Source

End

Seg.

Limit Limits

“00 - 11” = “0”

No

Chng.

= “1”

Source

Count

Start

Limit

“00 - 11”

Source

Count

End

Limit

“00 - 11”

Load

Dest.

Seg.

Count

= “0”

No

Chng.

= “1”

Destination

Seg. Count

Value

“00 - 11”

Load Source Seg.

Src. Count

Seg. Value

Count “00 - 11”

= “0”

No

Chng.

= “1”

Note: D15, D10, D5, and D2 read back as “0”s.

Table 6: Segment Control Register Bit Assignments

Segment Control Register (SC)

Device Select Register (DS)

The Segment Control register contains dual

independent incrementing counters with limits; one for

data reads and one for data writes. These counters

control which 16-bit segment of the 64-bit internal

resource is accessed during a particular data cycle on

the 16-bit data bus. The actual destination for data

writes and source for data reads (called the persistent

destination and source) are set independently with

SPD and SPS instructions, respectively. Either the

Foreground or Background Segment Control Register

will be active, depending on which has been selected,

and only the active Segment Control Register can be

written to or read from.

Each of the two counters consists of a start segment,

the end segment, and the current segment pointer. The

current segment pointer can be set to any segment

even if its a segment outside the range set by the start

and end segments. If a sequence of data writes or

reads is interrupted, the Segment Control register can

be reset to its inital start limits values using an RSC

instruction. A TCO SC instruction writes a configuration

value to the Segment Control register, as shown in

Table 6. After a Reset, both Source and Destination

counters are set to count from Segment 0 to Segment

3 with an initial value of 0. D15, D10, D5 and D2 always

read back as “0”s.

Page Address Register (PA)

The Page Address register is loaded by the user during

initialization with a TCO PA instruction followed by a

16-bit value (not FFFFH) which gives a unique address

to the different devices in a daisy-chain. In a

daisy-chain, the PA value of each device is loaded

followed by an SFF instruction to advance to the next

device as shown in the “Setting Page Address Register

Values” section. The Page Address register can be

read from the Status register. The lower five bits also

appear in the Next Free Address register. A software

Reset (TCO CT, OXXXH) does not affect the Page

Address register.

The Device Select register is used to select a specific

(target) device using the TCO DS instruction by setting

the 16-bit DS value equal to the target’s PA value. In a

daisy-chain, setting DS = FFFFH will select all devices.

However, in this case, the ability to read information out

of the device is restricted as shown in Tables 8a and 8b.

A software Reset (using the Control register) does not

affect the Device Select register.

Address Register (AR)

The Address register points to the CAM Memory

location to be operated upon with a M@[AR] or

M@aaaH instruction. It can be loaded directly by using

a TCO AR instruction or indirectly by using an

instruction requiring an absolute address, such as MOV

aaaH,CR,V. After being loaded, the Address register

value will then be used for the next memory access

referencing the Address register. After this access, the

Address register will automatically increment or

decrement from that value according to the setting of

CT3 and CT2 of the Control register. A Reset sets the

Address register to zero.

Either the Foreground or Background Address register

will be active, depending on which has been selected,

and only the active Address register will be written to or

read from.

Next Free Address Register (NF)

The Next Free Address in a system of MU9C3480L’s

can be read using a TCO NF instruction. Only the device

with /FI LOW and /FF HIGH will respond with its

contents of the Next Free Register, as shown in Table

7. The MU9C3480L automatically stores the address of

the first empty memory location in the Next Free

Address register, which is then used as a memory

address pointer for M@NF operations. The Full Flag

daisy chain causes only the device whose /FI input is

LOW and /FF output HIGH to respond to an instruction

using the Next Free address. After a Reset, the Next

Free Address register is set to zero.

Rev. 1.0 Draft Web

9

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