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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

FUNCTIONAL DESCRIPTION

The MU9C3480L LANCAM is a 256 x 64-bit

Content-addressable Memory (CAM) for network

address filtering, virtual memory, data compression,

cache, and table look-up applications. The MU9C3480L

contains 16,384 (16K) usable bits of static CAM,

organized as 256 64-bit Data fields. Each Data field can

be partitioned into a CAM and a RAM subfield on 16-bit

boundaries. The contents of the memory can be

randomly accessed or associatively accessed by the

use of a compare. During automatic Comparison cycles,

data in the Comparand register is automatically

compared with the “Valid” CAM section of the memory

array. The device ID of 341H can be read using a TCO

PS instruction.

The data inputs and outputs of the MU9C3480L

LANCAM are multiplexed for data and instructions over

a 16-bit I/O bus. Internally, data is handled on a 64-bit

basis, since the Comparand register, the Mask

registers, and each memory entry is 64 bits wide.

Memory entries are globally configurable into CAM and

RAM segments on 16-bit boundaries, as described in

US Patent 5,383,146 assigned to MUSIC

Semiconductors. Seven different CAM/RAM splits are

possible, with the CAM width going from one to four

segments, and the remaining RAM width going from

three to zero segments. Finer resolution on compare

width is possible by invoking a Mask register during a

compare, which does global masking on a bit basis. The

CAM subfield contains the Associative data which

enters into Compares, while the RAM subfield contains

the Associated data which is not compared. In LAN

Bridges, the RAM subfield could hold, for example,

port-address and aging information related to the

destination or source address information held in the

CAM subfield of a given location. In a translation

application, the CAM field could hold the dictionary

entries, while the RAM field holds the translations, with

almost instantaneous response.

results of the last comparison (Highest Priority Match or

Next free), or to an absolute address, or to the location

pointed to by the active Address register. Data can also

be written directly to the memory from the DQ bus using

any of the above addressing modes, with the Address

register directly loaded or set to increment or

decrement, allowing DMA-type reading or writing from

memory.

Two sets of configuration registers (Control, Segment

Control, Address, Mask Register 1, and the Persistent

Source and Destination) are provided to permit rapid

context switching between foreground and background

activities. Writes, reads, moves and compares are

controlled by the currently active set of configuration

registers. The foreground set would typically be

pre-loaded with values useful for comparing input data,

often called filtering, while the background set would be

pre-loaded with values useful for housekeeping

activities such as purging old entries. Moving from the

foreground task of filtering to the background task of

purging can be done by issuing a single instruction to

change the current set of configuration registers. The

match condition of the device is reset whenever the

active register set is changed.

The active Control register determines the operating

conditions within the device. Conditions set by this

register's contents are Reset, enable or disable Match

flag, enable or disable Full flag, default data translation,

CAM/RAM partitioning, disable or select masking

conditions, disable or select auto-incrementing or

-decrementing the Address register, and to set

1480-compatible or 2480-enhanced modes. The active

Segment Control register contains separate counters to

control the writing of 16-bit data segments to the

selected persistent destination, and to control the

reading of 16-bit data segments from the selected

persistent source.

Each entry has two validity bits (known as Skip bit and

Empty bit) associated with it to define its particular type:

Empty, Valid, Skip, or RAM. When data is written to the

active Comparand register and the active Segment

Control register reaches its terminal count, the contents

of the Comparand register are automatically compared

with the CAM portion of all the Valid entries in the

memory array. For added versatility, the Comparand

register can be barrel-shifted right or left one bit at a

time. A Compare instruction can then be used to force

another compare between the Comparand register and

the CAM portion of memory entries of any one of the four

validity types. After a Read or Move from Memory

operation, the validity bits of the location read or moved

will be copied into the Status register, where they can be

read from the Status register using Command Read

cycles.

There are two active Mask registers at any one time,

which can be selected to mask comparisons or data

writes. Mask Register 1 has both a foreground and

background mode to support rapid context switching.

Mask Register 2 does not have this mode, but can be

shifted left or right one bit at a time. For masking

comparisons, data stored in the active selected Mask

register determines which bits of the Comparand are

compared against the valid contents of the Memory. If

a bit is set HIGH in the Mask register, the same bit

position in the Comparand register becomes a “don't

care” for the purpose of the comparison with all the

memory locations. During a Write cycle, data in the

selected active Mask register can also determine which

bits in the destination will be updated. If a bit is HIGH in

the Mask register, the corresponding bit of the

destination is unchanged during the Write cycle.

Data can be moved from one of the data registers (CR, The Match line associated with each memory address

MR1, or MR2) to a memory location that is based on the is fed into a Priority encoder where multiple responses

Rev. 1.0 Draft Web

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