MU9C3480L-12DC Ver la hoja de datos (PDF) - Music Semiconductors

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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

FUNCTIONAL DESCRIPTION (CONT’D)

are resolved, and the address of the highest-priority

responder (the lowest numerical match address) is

generated. In the LAN Bridge application, a multiple

response might indicate an error. In other applications

the existence of multiple responders may be valid.

Control of these devices is via four input control signals

and by commands loaded into an Instruction decoder.

Two of the four input control signals determine the cycle

type. The control signals tell the device whether the

data on the I/O bus represents Data or a Command,

and is Input or Output. Commands are decoded by

Instruction logic and control moves, forced compares,

validity bit manipulations, and the data path within the

device. Registers (Control, Segment Control, Address,

Next Free Address, etc.) are accessed using

Temporary Command Override instructions. The data

path from the DQ bus to/from data resources

(Comparand, Masks, and Memory) within the device

are set until changed by Select Persistent Source and

Destination instructions.

if no match occurs during a comparison, read access to

the memory, and all the registers except the Next Free

Register, is denied to prevent device contention. In a

daisy chain, all devices will respond to Command and

Data Writes, depending on the conditions shown in

Tables 8a and 8b, unless the operation involves the

Highest Priority Match address or the Next Free

Address; in which case, only the specific device having

the Highest Priority Match or the Next Free Address will

respond.

A Page Address register in each device simplifies

vertical expansion in systems using more than one

LANCAM. This register is loaded with a specific device

address during system initialization, which then serves

as the higher-order address bits. A Device Select

register allows the user to target a specific device within

a vertically cascaded system by setting it equal to the

Page Address register value, or to address all the

devices in a string at the same time by setting the

Device Select value to FFFFH.

After a Compare cycle caused by either a Data Write to

the Comparand or Mask registers or a forced Compare,

the Status register contains the address of the Highest

Priority Matching location in that device, concatenated

with its Page Address, along with flags indicating

internal Match, Multiple Match, and Full. When the

Status register is read with a Command Read cycle, the

device with the Highest Priority match will respond,

outputting the System Match Address to the DQ bus.

The internal Match (/MA) and Multiple match (/MM)

flags are also output on pins. Another set of flags (/MF

and /FF) that are qualified by the match and full flags

of previous devices in the system are also available

directly on output pins, and are independently

daisy-chained to provide System Match and Full flags

in vertically cascaded LANCAM arrays. In such arrays,

Figure 2a shows expansion using a daisy-chain. Note

that system flags are generated without the need for

external logic. The Page Address register allows each

device in the vertically cascaded chain to supply its own

address in the event of a match eliminating the need for

an external Priority encoder to calculate the complete

Match address at the expense of the ripple-through time

to resolve the Highest-priority match. The Full flag

daisy-chaining allows Associative writes using a Move

to Next Free Address instruction which does not need

a supplied address.

Figure 2b shows an external PLD implementation of a

simple priority encoder to resolve the Highest-priority

match and gate the /E signal to each device for systems

requiring maximum performance.

DQ15–0

16

/E

/W

/CM

/EC

PA=0000h

Vcc

DQ15–0

/MI

/E

/FI

/W LANCAM

/CM

/FF

/EC

/MF

PA=0001h

DQ15–0

/MI

/E

/FI

/W LANCAM

/CM

/FF

/EC

/MF

/E

/GLOBAL

PLD

/E

LANCAM

/MA

/E

LANCAM

/MA

/E

LANCAM

/MA

PA=0007h

DQ15–0

/MI

/E

/FI

/W LANCAM

/CM

/FF

/EC

/MF

SYSTEM FULL

SYSTEM MATCH

Figure 2a: Vertical Cascading

5

/E

LANCAM

/MA

Figure 2b: External Prioritizing

Rev. 1.0 Draft Web

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