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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

OPERATIONAL OVERVIEW

To use the LANCAM, the user loads the data into the

Comparand register, which is automatically compared

to all valid CAM locations. The device then indicates

whether or not one or more of the valid CAM locations

contains data that matches the target data. The status

of each CAM location is determined by two validity bits

at each memory location. The two bits are encoded to

render four validity conditions: Valid, Skip, Empty, and

Random Access. The memory can be partitioned into

CAM and associated RAM segments on 16-bit

boundaries. By using one of the two available mask

registers, the CAM/RAM partitioning can effectively be

set at any arbitrary size between zero and 64 bits.

The MU9C3480L LANCAM's internal data path is 64

bits wide for rapid internal comparison and data

movement. A data translation facility converts between

IEEE 802.3 (CSMA/CD "Ethernet") and 802.5 (Token

Ring) address formats. Vertical cascading of additional

LANCAMs in a daisy-chain fashion extends the CAM

memory depth for large data bases. Cascading

requires no external logic. Loading data to the Control,

Comparand a mask registers automatically triggers a

compare, and compares may also be initiated by a

command to the device. Associated RAM data is

available immediately after a successful compare

operation. The Status register reports the results of

compares including all flags and addresses. Two mask

registers are available and can be used in two different

ways: to mask comparisons or to mask data writes. The

random access validity flag allows additional masks to

be stored in the CAM array where they may be

retrieved rapidly.

The device is controlled by a simple four-wire control

interface and commands loaded into the Instruction

decoder. A powerful instruction set increases the

control flexibility and minimizes software overhead.

Additionally, dedicated pins for match and

multiple-match flags enhance performance when the

device is controlled by a state machine. These and

other features make the LANCAM a powerful

associative memory that drastically reduces search

delays.

Skip Bit Empty Bit Entry Type

0

0

Valid

0

1

Empty

1

0

Skip

1

1

RAM

Table 1: Entry Types vs. Validity Bits

NC 7

DQ4 8

DQ5 9

NC 10

VCC 11

NC 12

GND 13

GND 14

DQ6 15

DQ7 16

NC 17

44-pin PLCC

(Top View)

39 /MA

38 /MI

37 /MF

36 GND

35 /RESET

34 VCC

33 VCC

32 NC

31 /E

30 /W

29 NC

Figure 1: Pinout Diagram

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active LOW. Inputs

(except for the RESET pin) should never be left floating. The CAM architecture draws large currents during compare operations,

mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.

DQ15-DQ0 (Data Bus, I/O, Three-state TTL)

/E (Chip Enable, Input, TTL)

The DQ15-DQ0 lines convey data, commands and status

to and from the MU9C3480L. The direction and nature of

the information that flows to or from the device is

controlled by the states of /W and /CM, respectively.

When /E is HIGH, DQ15-DQ0 go to Hi-Z.

The /E input enables the device while LOW. The falling

edge registers the control signals /W, /CM, /EC. The

rising edge locks the daisy chain, turns off the DQ pins,

and clocks the Destination and Source Segment

counters. The four cycle types enabled by /E are shown

in Table 2.

Rev. 1.0 Draft Web

2

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