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Número de pieza

componentes Descripción

Fabricante

56858

16-bit Digital Signal Controllers

Freescale Semiconductor 

Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA

Signal

Name

MISO

BGA LQFP

Pin No. Pin No.

B2

1

Type

Description

Input/Output

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device

is not selected. The driver on this pin can be configured as an

open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this

pin is configured for SPI operation.

GPIOF0

MOSI

C3

Input/Output Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

2

Input/

SPI Master Out/Slave In (MOSI)—This serial data pin is an output

Output (Z) from a master device and an input to a slave device. The master

device places data on the MOSI line a half-cycle before the clock edge

that the slave device uses to latch the data. The driver on this pin can

be configured as an open-drain driver by the SPI’s WOM bit when this

pin is configured for SPI operation.

GPIOF1

SCK

C2

Input/Output Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as input or output pin.

3

Input/Output SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit

rate clock for the SPI. This gated clock signal is an input to a slave

device and is generated as an output by a master device. Slave

devices ignore the SCK signal unless the SS pin is active low. In both

master and slave SPI devices, data is shifted on one edge of the SCK

signal and is sampled on the opposite edge where data is stable. The

driver on this pin can be configured as an open-drain driver by the

SPI’s WOM bit when this pin is configured for SPI operation. When

using Wired-OR mode, the user must provide an external pull-up

device.

GPIOF2

SS

D2

Input/Output Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

4

Input

SPI Slave Select (SS)—This input pin selects a slave device before a

master device can exchange data with the slave device. SS must be

low before data transactions and must stay low for the duration of the

transaction. The SS line of the master must be held high.

GPIOF3

XTAL

H2

EXTAL

G3

CLKO

L3

Input/Output Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

27

Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal

crystal oscillator output to an external crystal. If an external clock

source other than a crystal oscillator is used, XTAL must be used as

the input.

28

Input

External Crystal Oscillator Input (EXTAL)—This input should be

connected to an external crystal. If an external clock source other than

a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2

37

Output

Clock Output (CLKO)—This pin outputs a buffered clock signal.

When enabled, this signal is the system clock divided by four.

56858 Technical Data, Rev. 6

20

Freescale Semiconductor

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