56858 Ver la hoja de datos (PDF) - Freescale Semiconductor
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56858 Datasheet PDF : 64 Pages
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Introduction
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal
Name
TCK
TDI
TDO
TMS
BGA LQFP
Pin No. Pin No.
L8
60
K7
58
G6
57
J7
59
Type
Description
Input
Input
Output(Z)
Input
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Mode Select Input (TMS)—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
TRST
L7
56
Input
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment, since the
Enhanced OnCE/JTAG module is under the control of the debugger. In
this case it is not necessary to assert TRST when asserting RESET.
Outside of a debugging environment RESET should be permanently
asserted by grounding the signal, thus disabling the Enhanced
OnCE/JTAG module on the device.
Note: For normal operation, connect TRST directly to VSS. If the design is
to be used in a debugging environment, TRST may be tied to VSS through a
1K resistor.
56858 Technical Data, Rev. 6
Freescale Semiconductor
21
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