HEF4013B(2015) Ver la hoja de datos (PDF) - NXP Semiconductors.
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HEF4013B Datasheet PDF : 16 Pages
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Nexperia
6. Pinning information
6.1 Pinning
HEF4013B
Dual D-type flip-flop
Fig 3. Pin configuration
4
4
&3
&'
'
6'
966
9''
4
4
+()% &3
&'
'
6'
DDJ
6.2 Pin description
Table 2. Pin description
Symbol
1Q, 2Q
1Q, 2Q
1CP, 2CP
1CD, 2CD
1D, 2D
1SD, 2SD
VSS
VDD
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
7. Functional description
Description
true output
complement output
clock input (LOW to HIGH edge-triggered)
asynchronous clear-direct input (active HIGH)
data input
asynchronous set-direct input (active HIGH)
ground (0 V)
supply voltage
Table 3.
Control
nSD
H
L
H
L
L
Function table[1]
nCD
L
H
H
L
L
nCP
X
X
X
Input
nD
X
X
X
L
H
Output
nQ
nQ
H
L
L
H
H
H
L
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition.
HEF4013B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 10 December 2015
© Nexperia B.V. 2017. All rights reserved
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