AD28MSP01 Ver la hoja de datos (PDF) - Analog Devices
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AD28MSP01 Datasheet PDF : 28 Pages
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AD28msp01
V.32 TSYNC Mode
In V.32 TSYNC Mode, shown in Figure 7, the AD28msp01’s
transmit circuitry is synchronized to an external TSYNC signal.
The AD28msp01 receive circuitry is sampled synchronous to
the transmit circuitry, but the data can be resampled at a differ-
ent phase by using the resampling interpolation filter.
TCONV, TBIT and TBAUD are generated internally but are
phase-locked to the external TSYNC input signal with the digi-
tal phase-locked loop. RCONV, RBIT and RBAUD are gener-
ated internally (but frequency locked to TSYNC) and can be
phase adjusted with the Receive Phase Adjust Register (Control
Register 4).
TCONV initiates a new DAC sample update, loads the ADC
register (Data Register 2), and loads the DAC register (Data
Register 0) with a new sample.
The digital resampling interpolation filter can be used for digital
resampling of the received signal. Enable this function by setting
Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are
loaded into the interpolator at the TCONV rate and are resampled
at the RCONV rate.
When entering V.32 TSYNC Mode, RCONV is locked to
TCONV before TCONV is locked to TSYNC. If this mode is
entered from a non-V.32 mode, the device performs a soft reset.
The time required to lock TCONV to RCONV is dependent on
the phase difference between RCONV and TCONV when en-
tering the mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit rates, baud rates and
TSYNC rate can be set to any combination of clock rates listed
in the control register descriptions. The TSYNC field on Con-
trol Register 0 must be set to the frequency of the input pin.
Example
Transferring the following word sequence to the AD28msp01
will configure the device for V.32 TSYNC Mode at the clock
rates indicated:
Word
Transferred
Description
0x0000
0x0254
0x0002
0x0002
0x0003
0x0023
0x0001
0x0018
Control Register 0 address word
Enable interpolation filter, TSYNC = 7200,
sample rate = 7200, mode = V.32 TSYNC
Control Register 2 address word
RBAUD = 2400, RBIT = 7200
Control Register 3 address word
TBAUD = 1200, TBIT = 4800
Control Register 1 address word
Configure and power-up device
ANALOG IN
MCLK
TSYNC
ANALOG OUT
16
A/D
DATA
REGISTER 2
TX CLOCKS
TCONV
TBIT
TBAUD
PHASE ADJUST
CONVERT
START
DIGITAL PHASE
LOCKED LOOP
AD28msp01
16
RXRCXLCOLCOKCSKS
RCONV
RBIT
RBAUD
PHASE ADJUST
CONTROL
REGISTER 4
RX PHASE ADJUST
INTERPOLATION
FILTER
DATA
REGISTER 1
16
PHASE
ADJUST
16
DATA
REGISTER 3
16
D/A
DATA
16
REGISTER 0
DSP Processor
16
ECHO
CANCELLATION
16
TO MODEM RX
FROM MODEM TX
Figure 7. V.32 TSYNC Mode Block Diagram
REV. A
–11–
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