AD28MSP01 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD28MSP01

PSTN Signal Port

Analog Devices 

ANALOG IN

MCLK

ANALOG OUT

AD28msp01

16

A/D

DATA

REGISTER 2

16

RTX CLOOCCKKSS

RCONV

RBIT

RBAUD

PHASE ADJUST

TX CLOCKS

TCONV

TBIT

TBAUD

PHASE ADJUST

CONVERT

START

CONTROL

REGISTER 4

RX PHASE ADJUST

CONVERT

START

CONTROL

REGISTER 5

TX PHASE ADJUST

16

D/A

DATA

16

REGISTER 0

AD28msp01

DSP Processor

TO MODEM RX

FROM MODEM TX

Figure 11. Asynchronous Fallback Mode Block Diagram

Operating Mode Summary

Table III summarizes the operating modes.

Table III. Operating Mode Summary

Mode

Initial Phase

Phase Adjust

Lock After

Normal DPLL* Register

Resampling

Entering Mode Operation

Programmable† Interpolator

Internal Filter

Operation

Synchronous To:

ADC DAC

Control

Register 0

OP 2-0

Async Fallback

Async TSYNC

V.32 TSYNC

no phase lock

TCONV lock

to TSYNC

RCONV lock

to TCONV

no phase lock

TCONV lock

to TSYNC

TCONV lock

to TSYNC

RCV, TX

RCV

RCV

V.32 Internal Sync RCONV lock

to TCONV

no phase lock

RCV, TX

V.32 Loopback TCONV lock

to RCONV

no phase lock

RCV††

not used

not used

RCONV TCONV 0 0 0

RCONV TCONV 1 1 1

Input synchronous TCONV

and in phase with

TCONV, Output

synchronous and in

phase with RCONV

TCONV

100

Input synchronous TCONV

and in phase with

TCONV, Output

synchronous and in

phase with RCONV

TCONV

101

not used

TCONV TCONV 1 1 0

NOTES

*DPLL—Digital Phase-Locked loop.

†RCV phase adjusted via Control Register 4, TX phase adjusted via Control Register 5.

††Adjusting RCV phase also adjusts TX phase in this mode.

Note: All receive clocks: RBIT, RBAUD are synchronous to RCONV. All transmit clocks: TBIT, TBAUD are synchronous to TCONV.

REV. A

–15–

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