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AD28MSP01

PSTN Signal Port

Analog Devices 

AD28msp01

Asynchronous Fallback TSYNC Mode

The Asynchronous Fallback TSYNC Mode is shown in Figure

10. TCONV, TBIT and TBAUD are generated internally but

phase locked to the external TSYNC input signal. RCONV,

RBIT and RBAUD are generated internally and can be phase

adjusted with the Receive Phase Adjust Register (Control

Register 4).

This mode is entered by setting the Operating Mode field in

Control Register 0. The RCONV/TCONV rate can be set to

9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field

in Control Register 0. The TBIT and TBAUD clock rates are

set by adjusting the appropriate bits in Control Register 3. The

RBIT and RBAUD clock rates are set by adjusting the appropri-

ate bits in Control Register 2. The bit rates, baud rates and

TSYNC rate can be set to any combination of clock rates listed

in the control register descriptions.

ANALOG IN

MCLK

TSYNC

AD28msp01

16

A/D

DATA

16

REGISTER 2

RTX CLOOCCKKSS

RCONV

RBIT

RBAUD

PHASE ADJUST

TX CLOCKS

TCONV

TBIT

TBAUD

PHASE ADJUST

CONVERT

START

CONTROL

REGISTER 4

RX PHASE ADJUST

DIGITAL PHASE

LOCKED LOOP

DSP Processor

TO MODEM RX

ANALOG OUT

D/A

16

DATA

REGISTER 0

16

FROM MODEM TX

Figure 10. Asynchronous Fallback TSYNC Driven Mode Block Diagram

Asynchronous Fallback Mode

The Asynchronous Fallback Mode is shown in Figure 11.

TCONV, TBIT and TBAUD are generated internally and can

be phase adjusted with the Transmit Phase Adjust Register

(Control Register 5). RCONV, RBIT and RBAUD are gener-

ated internally and can also be phase adjusted with the Receive

Phase Adjust Register (Control Register 4). The digital phase-

locked is not used in this operating mode.

This mode is entered by setting the Operating Mode field in

Control Register 0. The RCONV/TCONV rate can be set to

9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field

in Control Register 0. The TBIT and TBAUD clock rates are

set by adjusting the appropriate bits in Control Register 3. The

RBIT and RBAUD clock rates are set by adjusting the appropri-

ate bits in Control Register 2. The bit and baud rates can be set

to any combination of clock rates listed in the control register

descriptions.

–14–

REV. A

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