HSP50215 Ver la hoja de datos (PDF) - Intersil
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HSP50215 Datasheet PDF : 21 Pages
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HSP50215
AC Electrical Specifications VCC = 5 ±5%, TA = 0oC to 70oC, Commercial; TA = -40oC to 85oC, Industrial (Note 5)
52MHz
PARAMETER
SYMBOL
MIN
MAX
UNITS
REFCLK Clock Period (Commercial)
REFCLK Clock Period (Industrial)
REFCLK High
REFCLK Low
Setup Time CAS(15:0), SYNCIN to REFCLK
Hold Time CAS(15:0), SYNCIN to REFCLK
Setup Time A(9:0) to Rising Edges of WR or CE Low
Setup Time C(15:0) to Rising Edges of WR or CE Low
Hold Time A(9:0) to Rising Edges of WR or CE Low
Hold Time C(15:0) to Rising Edges of WR or CE Low
Read Address Low to Data Valid
Rising Edge of WR or CE to FIFORDY High (FIFO Write)
REFCLK to OUT(15:0)
REFCLK to SYNCOUT, SAMPCLK and FIFORDY Valid
WR High
WR Low
RD Low
RD LOW and CE LOW to Data Valid
RD HIGH and CE HIGH to Output Disable
t CP
19
-
ns
t CP
21
-
ns
t CH
7
-
ns
t CL
7
-
ns
t DS
6
-
ns
t DH
1
-
ns
t AS
12
-
ns
t CS
6
-
ns
t AH
2
-
ns
t CH
2
-
ns
t ADO
-
16
ns
t WF
12
-
ns
t DO
-
8
ns
t DOC
-
12
ns
t WRH
7
-
ns
t WRL
7
-
ns
t RL
9
-
ns
t RDO
-
8
ns
t ROD
-
10
ns
(Note 6)
Output Enable Time
Output Disable Time
t OE
-
7
ns
t OD
-
8
ns
(Note 6)
Output Rise, Fall Time
t RF
-
5
ns
(Note 6)
NOTE:
5. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -400µA. Input reference level for CLK is 2.0V, all other inputs 1.5V.
Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
DUT
S1
CL †
SWITCH S1 OPEN FOR ICCSB AND ICCOP
† TEST HEAD CAPACITANCE
±
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
3-441
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