HSP50215 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HSP50215

Digital UpConverter

Intersil 

HSP50215

BIT

POSITION

15-0

FUNCTION

Reserved (Note 1)

CONTROL ADDRESS 20: SPARE

Reserved (Note 1).

DESCRIPTION

BIT

POSITION

15-0

FUNCTION

Reset

CONTROL ADDRESS 21: RESET CONTROL

DESCRIPTION

RST. Writing to this registers will reset this part.

BIT

POSITION

15-2

1

FUNCTION

Reserved (Note 1)

External Sync Polarity

CONTROL ADDRESS 22: SYNC CONTROL

DESCRIPTION

Reserved (Note 1).

SYNCPOL.

0 defines a Sync assertion as a transition from a logic low to a logic high; 1 defines a Sync assertion

as a transition from a logic high to a logic low:

0=

1=

0

Sync Select

SYNCSEL. 0 = Sync via a Write to Control Word 3; 1 = Sync via SYNCIN control input.

BIT

POSITION

15-0

FUNCTION

Reserved (Note 1)

CONTROL WORDS 23: TEST CONTROL

Reserved (Note 1).

DESCRIPTION

BIT

POSITION

15:0

CONTROL WORDS 512-767: I CHANNEL POLY-PHASE COEFFICIENTS 512-767 (0X200H = 0X2FFH)

FUNCTION

I Coefficients

DESCRIPTION

ICOEFFICIENTS(15:0). Coefficients are loaded from the first coefficient (C0) in address 0x200h to the

last address in 0x2FFh. The convolution multiplies C0 by the most recent data sample. For a 16 tap,

interpolate-by-4 filter, the calculations are:

OUTPUT0 = (C0*D[n]) + (C4*D[n-1]) + (C8*D[n-2]) + (C12*D[n-3]).

OUTPUT1 = (C1*D[n]) + (C5*D[n-1]) + (C9*D[n-2]) + (C13*D[n-3]).

OUTPUT2 = (C2*D[n]) + (C6*D[n-1]) + (C10*D[n-2]) + (C14*D[n-3]).

OUTPUT3 = (C3*D[n]) + (C7*D[n-1]) + (C11*D[n-2]) + (C15*D[n-3]).

See Microprocessor Write section for more detail.

CONTROL WORDS 768-1023: Q CHANNEL POLY-PHASE COEFFICIENTS 768-1023 (0X300H = 0X3FFH)

BIT

POSITION

FUNCTION

DESCRIPTION

15:0

Q Coefficients

QCOEFFICIENTS(15:0). Coefficients are loaded from the first coefficient (B0) in address 0x300h to

the last address in 0x3FFh. The convolution multiplies B0 by the most recent data sample. For a 16

tap, interpolate-by-4 filter, the calculations are:

OUTPUT0 = (B0*D[n]) + (B4*D[n-1]) + (B8*D[n-2]) + (B12*D[n-3]).

OUTPUT1 = (B1*D[n]) + (B5*D[n-1]) + (B9*D[n-2]) + (B13*D[n-3]).

OUTPUT2 = (B2*D[n]) + (B6*D[n-1]) + (B10*D[n-2]) + (B14*D[n-3]).

OUTPUT3 = (B3*D[n]) + (B7*D[n-1]) + (B11*D[n-2]) + (B15*D[n-3]).

See Microprocessor Write section for more detail.

NOTE:

1. Reserved bits should be set to logic 0.

3-439

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