HSP50215 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HSP50215

Digital UpConverter

Intersil 

HSP50215

DS0

IP0 768 =

D0

IP1 769 =

D1

IP2 770 =

D2

IP3 771 =

D3

IP4 772

IP5 773

IP6 774

IP7 775

IP8 776

IP9 777

IP10 778

IP11 779

IP12 780

IP13 781

IP14 782

IP15 783

TABLE 7. Q COEFFICIENT ADDRESSING FOR A 16 TAP INTERPOLATED BY 4 FILTER

DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12

784 = 800 = 816 = 832 848 864 880 896 912 928 944 960

D4 D8 D12

785 = 801 = 817 = 833 849 865 881 897 913 929 945 961

D5 D9 D13

786 = 802 = 818 = 834 850 866 882 898 914 930 946 962

D6 D10 D14

787 = 803 = 819 = 835 851 867 883 899 915 931 947 963

D7 D11 D15

788 804 820 836 852 868 884 900 916 932 948 964

789 805 821 837 853 869 885 901 917 933 949 965

790 806 822 838 854 870 886 902 918 934 950 966

791 807 823 839 855 871 887 903 919 935 951 967

792 808 824 840 856 872 888 904 920 936 952 968

793 809 825 841 857 873 889 905 921 937 953 969

794 810 826 842 858 874 890 906 922 938 954 970

795 811 827 843 859 875 891 907 923 939 955 971

796 812 828 844 860 876 892 908 924 940 956 972

797 813 829 845 861 877 893 909 925 941 957 973

798 814 830 846 862 878 894 910 926 942 958 974

799 815 831 847 863 879 895 911 927 943 959 975

DS13

976

977

978

979

980

981

982

983

984

985

986

987

988

989

990

991

DS14

992

993

994

995

996

997

998

999

1000

1001

1002

1003

1004

1005

1006

1007

DS15

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021

1022

1023

TABLE 8. READ ADDRESS MAP FOR MICRO PROCESSOR INTERFACE

A4

A2

A1

A0

DESCRIPTION

0

X

0

0

Carrier Center Frequency: CF(31:16)

0

X

0

1

Carrier Center Frequency: CF(15:0)

0

X

1

0

Re-Sampler Center Frequency: SF(29:16)

0

X

1

1

Re-Sampler Center Frequency: SF(15:0)

1

0

0

0

Modulation Control: En Out bit 3; Mod(2:0)

1

0

0

1

Gain Control: OUTGAIN(7:0)

1

0

1

0

FIFO Control: FIFO Ready bit 5; I FIFO Empty bit 4; Q FIFO Empty bit 3; RTH(2:0)

1

0

1

1

Poly-Phase Control: DS(3:0) = b5-2; IP(1:0)

1

1

0

X

EnNCO

1

1

1

0

Sync Control: Ext Sync Polarity bit 1; Sync Sel bit 0

1

1

1

1

Test Control

FIFO Ready is the logical inverse of the FIFORDY output. I and Q FIFO empty bits are the output of a “zero” state detector operating on the

address bus for the respective FIFO.

WR

RD

DON’T CARE

A(9:0)

1000

1001

1010

1011

C(15:0)

HI-Z

READ HI-Z READ HI-Z READ HI-Z READ HI-Z

NOTE: See Table 8 for valid Read Addresses.

FIGURE 15. TYPICAL READ SEQUENCE

3-435

Share Link: