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CMX980AL7

Digital Radio Baseband Processor

MX-COM Inc  

Digital Radio Baseband Processor

11

CMX980A Advance Information

4.3.8 Symbol Clock Phase Adjustment

In order to comply with the requirement to maintain the phase error between the Mobile Station (MS) and

Base Station (BS) symbol clock to less than ±1/4 symbol time, a mechanism to allow phase adjustment of the

CMX980A symbol clock is provided.

This phase adjustment is achieved by writing a command to the SymClkPhase Register, which allows

adjustment in steps of ±1/4 or ±1/8 symbol times. It is intended that the user determine the symbol clock

phase of the BS after clock recovery has been performed on the received data. Then, allowing for the fixed Tx

path delay, the CMX980A phase can be advanced or retarded until it is within the specified error limit. The

internal symbol clock phase can be accessed by allowing the symbol clock reference signal to appear on the

N_IRQ pin, or alternatively using the I/Q identification mode (see Section 4.7.3) which places the symbol

clock in the Rx I channel LSB. Thus via hardware or software means the internal Tx symbol clock reference

time can be determined and the phase with respect to the BS adjusted.

4.3.9 Direct Write to Tx 79-tap Filter Input

A mechanism to allow direct write to the I and Q Tx 79-tap filter inputs at the symbol rate is provided for use in

systems where a different modulation scheme is to be employed. See Section 4.7.4 for further details.

4.3.10 Test Access to DAC Input

A mechanism to allow read and write access to DAC input data is provided for use in testing or in other

systems where the modulator and filter blocks are not required. By operating the serial port at the high serial

clock rate and without a frame gap, it is possible to provide only half of the normal bit rate for two channels,

thus data can be provided at MCLK/64 for a single channel or MCLK/128 for both channels. The user should

provide the appropriate data at the required sample rate (MCLK/64 or MCLK/128) via the serial interface,

which will be transferred to the DAC logic at the next internal sample clock after the data is written to the

register. Write operations to the upper and lower byte register and I and Q channels must be synchronized in

phase by the user to the sample clock strobe. This is to avoid splitting the I and Q channel or upper and lower

bytes into different samples. The phase of the sample clock can be determined by allowing the Symbol Clock

(which is in phase with the internal sample clock but 1/8 of the rate) to appear on the N_IRQ pin.

Note that data input at this point will have to be pre-filtered to compensate for the reconstruction filter droop

(approximately 2dBs at MCLK/1024), which is normally compensated by the internal FIR default coefficients.

In addition, data input at a MCLK/128 sample rate will have a sinx/x alias around MCLK/128, which will be

reduced to about 65dBs below the wanted signal by the reconstruction filter. There is some scope to improve

this by enhancing the recommended single pole filter stage on the Tx output, but any adverse change in the

in-band gain and group delay performance will have to be compensated prior to loading the data into the IC.

4.4 Rx Data Path

4.4.1 Anti-Alias Filtering and Sigma-Delta A-D Converters

The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high over-sampling rate relaxes the

design requirements on the anti-alias filter. However, to achieve optimum performance the anti-alias filter

must reject the sampling frequency to about -110dB, of which at least 30dB must be provided externally.

Additionally, in order to ease the complexity of the subsequent digital filters, there is a further requirement that

the anti-alias filter suppress 8x symbol rate to about -15dB. The on-chip anti-alias filter is designed to achieve

this when used in conjunction with some external filtering. If required, the on-chip anti-alias filter can be by-

passed and powered down, although external anti-aliasing must then be provided. The fourth-order Sigma-

Delta A-D converters are designed to have low distortion and >96dB dynamic range. The baseband I and Q

channels must be provided as differential signals; this minimizes in-band pick up both on and off the chip.

Both I and Q Sigma-Delta converters produce a single bit output sampled at MCLK/4. This data is passed to a

non-programmable decimation FIR filter, which is sampled at MCLK/4 and gives sufficient rejection at 8x

symbol rate (MCLK/64) to permit decimation to that frequency (note that around -30dB is provided by the

primary anti-alias filters).

4.4.2 Rx FIR Filters

Digital filtering is applied to the data from the Sigma-Delta A-D converter decimation filters by two 63-tap FIR

filters in cascade. The default coefficients are set to give a Root Raised Cosine response with roll-off factor

(α) of 0.35. The first filter is used to enhance stop-band rejection, while the second filter provides the primary

shaping requirements for root raised cosine response.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. 20480201.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA

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