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CMX980AL7

Digital Radio Baseband Processor

MX-COM Inc  

Digital Radio Baseband Processor

17

CMX980A Advance Information

4.7.5.1 Indirect Memory Addressing

All internal memory access is via an access point. First, a command word access is used to reset the internal

address pointer, then data port access operations post-increment this address pointer.

Example: To program the fifth and sixth locations of the Auxiliary SRAM with $0x01AA, the commands

would be:

$0x8000⇒Cmd

$0x8118⇒Cmd

$0x7300⇒Cmd

CmdRd⇒$0x73xx

$0xF002⇒Cmd

$0xF16A⇒Cmd

$0x7000⇒Cmd

CmdRd⇒$0x7002

$0x7100⇒Cmd

CmdRd⇒$0x716A

$0x8110⇒Cmd

; set ConfigCtrl1 all bits Low

; set ConfigCtrl2 bits 7 and 6 Low

; set ConfigCtrl2 bit 4 High

; set ConfigCtrl2 bit 3 High

; read SramData LSB Register

; SramData LSB Register data returned

; write SramData LSB Register

; write SramData MSB Register

; read SramData LSB Register

; SramData LSB Register data returned

; read SramData MSB Register

; SramData MSB Register data returned

; set ConfigCtrl2 bit 3 Low

; use default conditions

; required for Page 0 addressing.

;

post-increment addresses on a read

operation

;

enable read/write access to the

Auxiliary SRAM

;

read fourth memory location (LSB).

Post-increment pointer.

; discard this byte

;

write $0x02 to fifth memory location

(LSB)

;

write $0x6A to sixth memory location

(MSB)

; read fifth memory location (LSB)

; check this byte is $0x02

; read sixth memory location (MSB)

; check this byte is $0x6A

;

disable read/write access to the

Auxiliary SRAM

4.7.6 Coefficient Memory

The convention for naming filter coefficients is A1 to An, where n is given by the filter tap length, i.e. for a

63-tap filter, n = 63. Within the filter architecture, location A0 has a special purpose and must contain zero for

correct operation of the computational algorithm. The internal architecture of the 63-tap filters allows access

to all coefficients, but the default values are symmetrical about the central coefficient to provide linear phase

response. The user is free to write non-symmetrical values, giving the possibility of non-linear phase

correction for off-chip components in these filters. The Tx 79-tap filter differs by having coefficients A1 to

A40 only, taking advantage of the filter symmetry to reduce its RAM size. Thus write or read operations

beyond the A40 coefficient number will be reflected about the central coefficient e.g. the 47th read operation

from the 79-tap filter would access coefficient location A33 (80-47).

To access the coefficient RAMs, the user asserts the CoeffRamIoEn bit in the ConfigCtrl2 Register, then

performs the operation (read or write) to the MSB of the required FIR filter. The first access after the

CoeffRamIoEn bit goes high is directed to location A1. Completing the coefficient access, by addressing the

LSB, automatically moves the Coefficient Ram Pointer to A2. The process is repeated until the required

number of locations has been accessed.

There is no practical reason to write or read beyond location A40 in the 79-tap filter, but in any case the user

must avoid write operations at the (Filter Length + 1) location in any filter. As previously stated this location

must be zero for the filters to operate correctly.

Note that filter coefficient read/write operations should be performed with the appropriate path (Tx or Rx)

disabled, but the clock stop bits must NOT be set.

The global reset (N_RESET pin) forces the default coefficients in all filters when asserted (Low).

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. 20480201.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA

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