CMX980AL7 Ver la hoja de datos (PDF) - MX-COM Inc

Número de pieza

componentes Descripción

Fabricante

CMX980AL7

Digital Radio Baseband Processor

MX-COM Inc  

Digital Radio Baseband Processor

18

CMX980A Advance Information

4.7.7 Auto Power Save Mode

By setting the AutoClkStopMode bit in the ClkStopCtrl Register, the serial interface will enter an automatic

power down mode. In this mode, if no serial port activity on the CmdFS is detected after a time out (TMO)

period the serial interface will enter a standby state. In this state all master clock activity within the interface is

stopped (to reduce power to a minimum) and the SClk pin stops in the high state. It will remain in this state

until the user asserts the CmdFS pin for at least one MCLK cycle time, when normal serial port activity will

recommence and serial port operation can continue as normal. Subsequent periods of TMO without CmdFS

activity will cause the serial interface to enter power down mode again.

The time out period TMO is fixed internally to 4096 master clock periods (444µs when using a 9.216MHz

master clock).

When in the power down state and the SClk pin is high, the CmdFS pin may be asserted asynchronously but,

when the SClk re-starts, subsequent CmdFS strobes must respect the timing constraints given in the timing

section of this document. The serial interface is stopped in the state where it tests the CmdFS pin for a high

state, so re-starting from this point by asserting CmdFS will begin a serial operation cycle in the interface

logic.

Applying global reset while in the power down state will return the device to normal serial mode.

The use of Auto Power Save mode, by setting the AutoClkStopMode bit, is available only in low data rate

mode (set DataRateHi bit of ConfigCtrl1 Register inactive), as this mode is envisaged for use in low

speed/low power applications. However, systems that use high data rate mode can make use of this facility

by setting a low data rate (set DataRateHi bit of ConfigCtrl1 Register inactive) before asserting the

AutoClkStopMode bit, then returning to the high data rate mode by setting the DataRateHi bit active.

4.8 Register Description

This section describes in detail each of the registers and access points addressed by the Command Control

Serial Word.

4.8.1 Key to Register Map

Each section that follows describes in detail the operation and use of each of the registers in the device. The

registers are split into their functional groups, grouping associated registers together. Each section consists of

a Title, an Address, a Function Reference Field, a Description, and a Bit Specification.

The Function Reference Field describes the overall access available to this section (RW/W/R, where

R = Read and W = Write).

The Bit Specification describes the function of each individual bit, or a range of bits within a register. There is

a separate line for each distinct field of bits. The State column indicates the action available to each group of

bits (RW/W/R). Address and data format illustrations show the bit positions in multiple-byte transfers. “R”

indicates a reserved bit, which should be set to logic zero when writing. Its value is undefined when read. “X”

indicates a don’t know/don’t care state.

4.8.2 Register Reset State

All I/O access points (both read and write) are reset to logic zero on taking N_RESET Low, except where

explicitly shown in this document. The reset state of status bits will depend on the level of the status signal

being monitored. Other registers (both read and write) are not affected by taking N_RESET Low.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. 20480201.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA

All trademarks and service marks are held by their respective companies

Share Link: