TRC105 Ver la hoja de datos (PDF) - RF Monolithics, Inc
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TRC105 Datasheet PDF : 67 Pages
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2.6 PLL Loop Filter
The loop filter for the frequency synthesizer is shown in Figure 6.
PLL Loop Filter
Figure 6
PLL Loop Filter Components
Name
C8
C9
R1
Value
1000 pF
6800 pF
6.8 kΩ
Tolerance
±10%
±10%
±5%
Table 6
Recommended component values for the frequency synthesizer loop filter are provided in Table 6. The loop filter
settings are not dependent on the frequency band, so they can be used on all designs. PLL lock status can be
provided on Pin 23 by setting the IRQCFG0E_PLL_LOCK_EN[0] bit to a 1. Pin 23 goes high when the PLL is
locked. The lock status of the PLL can also be checked by reading the IRQCFG0E_PLL_ LOCK_ST[1] bit. This
bit latches high each time the PLL locks and must be reset by writing a 1 to it.
3.0 Operating Modes
The TRC105 has 5 possible chip-level modes. The chip-level mode is set by MCFG00_Chip_Mode[7..5], which
is a 3-bit pattern in the configuration register. Table 7 summarizes the chip-level modes:
MCFG00_Chip_Mode[7..5]
000
001
010
011
100
Chip-level Mode
Sleep
Standby
Synthesizer
Receive
Transmit
Enabled Functions
None
Crystal oscillator
Crystal and frequency synthesizer
Crystal, frequency synthesizer and receiver
Crystal, frequency synthesizer and transmitter
Table 7
Table 8 gives the state of the digital pins for the different chip-level modes and settings:
PIN Function
nSS_CONFIG*
nSS_DATA*
IRQ0
IRQ1
DATA
CLKOUT
SDO**
SDI
SCK
Sleep
Mode
I
I
TRI
TRI
TRI
TRI
TRI/O
I
I
Standby
Mode
I
I
O
O
TRI
O
TRI/O
I
I
Synthesizer
Mode
I
I
O
O
TRI
O
TRI/O
I
I
Receive
Mode
I
I
O
O
O
O
TRI/O
I
I
I = Input, O = Output, TRI = High Impedance
*nSS_CONFIG has priority OVER nSS_DATA
**SDO is an output if nSS CONFIG = 0 and/or nSS DATA = 0
Table 8
Transmit
Mode
I
I
O
O
I
O
TRI/O
I
I
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Page 11 of 67
TRC105 - 10/16/12
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