TRC105 Ver la hoja de datos (PDF) - RF Monolithics, Inc
Número de pieza
componentes Descripción
Fabricante
TRC105 Datasheet PDF : 67 Pages
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S ta r t P a tte r n D e te c tio n T im in g
D A TA
B it 0
B it 1
B it N -1
B it N
B it N + 1
D C LK
PA TTER N
D ETEC T
Figure 9
Note that start pattern detection is enabled only if data and clock recovery is enabled.
3.4 RSSI
The received signal strength is measured in the amplifier chains behind the second mixers. Each amplifier chain
is composed of 11 amplifiers each having a gain of 6 dB and an intermediate output at 3 dB. By monitoring the
two outputs of each stage, an estimation of the signal strength with a resolution of 3 dB and a dynamic range of
63 dB is obtained. This estimation is performed 16 times over a period of the I and Q signals and the 16 samples
are averaged to obtain a final RSSI value with a 0.5 dB step. The period of the I and Q signal is the inverse of the
deviation frequency, which is the low-IF frequency in OOK mode. The RSSI effective dynamic range can be in-
creased to 70 dB by adjusting MCFG01_IF_Gain[1..0] for less gain on high signal levels.
The RSSI block can also be used in interrupt mode by setting the bit IRQCFG0E_RSSI_Int[3] to 1. When
RXCFG14_RSSI is equal or greater than a predefined value stored in IRQCFG0F_RSSI_thld, bit IRQCFG0E_
SIG_DETECT[2] goes high and an interrupt signal RSSI_IRQ is generated on pin IRQ0 if IRQCFG0D_RX_
IRQ0[7..6] is set to 01 (see Table 10). The interrupt is cleared by writing a 1 to bit IRQCFG0E_ SIG_DETECT[2].
If the bit RSSI_IRQ remains high, the process starts again. Figure 10 shows the timing diagram of RSSI in inter-
rupt mode.
T R C 1 0 5 R S S I In te r r u p t O p e r a tio n
R S S I T h r e s h o ld S e t to 3 0
IR Q C F G 0 E B it 3
(R S S I_ In t)
R X C FG 14
(R S S I V a lu e )
X
X
22
28
26
31
29
25
25
33
31
21
24
22
X
IR Q C F G 0 E B it 2
(S IG _ D E T E C T )
In te r r u p t
D e te c te d
In te r r u p t
R eset
In te r r u p t
D e te c te d
In te r r u p t
R eset
3.5 Receiving in Buffered Data Mode
Figure 10
The receiver works in Buffered data mode when the MCFG01_Mode[7..6] bits are set to 01. In this mode, the
output of the data and clock recovery, i.e., the demodulated and resynchronized signal and the clock signal DCLK
are not sent directly to the output pins DATA and IRQ1 (DCLK). These signals are used to store the demodulated
data in blocks of 8 bits in a 64-byte FIFO. Figure 11 shows the receiver chain in this mode. The FSK and OOK
demodulators, data and clock recovery circuit and start pattern detect block work as described for Continuous
data mode, but they are used with two additional blocks, the FIFO and SPI.
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Page 15 of 67
TRC105 - 10/16/12
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