TRC105 Ver la hoja de datos (PDF) - RF Monolithics, Inc

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Fabricante

TRC105

300-510 MHz RF Transceiver

RF Monolithics, Inc 

T R C 1 0 5 B u ffe r d & P a c k e t M o d e D e m o d u la tio n

R S S I_ IR Q

RSSI

IF A m p lifie r

L im ite r

IF A m p lifie r

L im ite r

OOK

D e te c to r

FSK

D e te c to r

F S K /O O K

D a ta &

C lo c k

R e c o v e ry

RECO G

R X _ IR Q 0

S ta rt

P a tte rn

D e te c t

PA TTER N

W r ite _ B y te

IR Q 0

n F IF O E M P T Y

D A TA

R X _ IR Q 1

F IF O

F IF O F U L L

IR Q 1

F IF O _ In t

S P I_ ld

F IF O _ r d R S S I_ IR Q

SDI

SPI

SDO

Figure 11

SCK

nS S _D A TA

When the TRC105 is in receive mode and MCFG01_Mode [7..6 ] bits are set to 01, all of the blocks described

above are enabled. In a normal communication frame the data stream is comprised of a 24-bit preamble, a start

pattern and data. Upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the

preamble and start pattern, and stores the data in the FIFO for retrieval by the host microcontroller. This automat-

ed data extraction reduces the loading on the host microcontroller.

The IRQCFG0E_Start_Fill[7] bit determines how the FIFO is filled. If IRQCFG0E_Start_Fill[7] is set to 0, data

only fills the FIFO when a start pattern is detected. Received data bits are shifted into the pattern recognition

block which continuously compares the received data with the contents of the SYNCFG registers. If a match oc-

curs, the start pattern detect block output is set for one bit period and the IRQCFG0E_Start_Det[6] bit is also set.

This internal signal can be mapped to the IRQ0 output using interrupt signal mapping. Once a pattern match has

occurred, the start pattern detect block will remain inactive until the IRQCFG0E_Start_Det[6] bit is reset.

If IRQCFG0E_Start_Fill[7] is set to 1, FIFO filling is initiated by asserting IRQCFG0E_Start_Det[6]. Once 64

bytes have been written to the FIFO the IRQCFG0D_FIFOFULL[1] signal is set. Data should then be read out. If

no action is taken, the FIFO will overflow and subsequent data will be lost. If this occurs the IRQCFG0E_FIFO_

OVR[4] bit is set to 1. The IRQCFG0D_FIFOFULL[1] signal can be mapped to pin IRQ1 as an interrupt for a mi-

crocontroller if IRQCFG0D_RX_IRQ1[5..4] is set to 01. To recover from an overflow, a 1 must be written to

IRQCFG0D_ FIFO_OVR[4]. This clears the contents of the FIFO, resets all FIFO status flags and re-initiates pat-

tern detection. Pattern detection can also be re-initiated during a FIFO filling sequence by writing a 1 to

IRQCFG0E_Start_Det[6].

The details of the FIFO filling process are shown in Figure 12. As the first byte is written into the FIFO, signal

IRQCFG0D_nFIFOEMPY[0] is set indicating at least one byte is present. The host microcontroller can then read

the contents of the FIFO through the SPI interface. When all data is read from the FIFO, IRQCFG0D_

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TRC105 - 10/16/12

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