T431616D Ver la hoja de datos (PDF) - Taiwan Memory Technology

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componentes Descripción

Fabricante

T431616D

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616D/E

LVTTL Interface

Reference Level of Output Signals

Output Load

Input Signal Levels

Transition Time (Rise and Fall) of Input Signals

Reference Level of Input Signals

1.4V / 1.4V

Reference to the Under Output Load (B)

2.4V / 0.4V

1ns

1.4V

Output

30pF

3.3V

1.2kΩ

870Ω

Output

Z0= 50 Ω

1.4V

50Ω

30pF

LVTTL D.C. Test Load (A)

LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns).

8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.

9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows:

the number of clock cycles = specified value of timing/Clock cycle time

(count fractions as a whole number)

10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.

11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns

If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be

added to the parameter.

12. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both

CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.

2) After power-up, a pause of 200us minimum is required. Then, it is recommended that LDQM/UDQM is held

"HIGH" (VDD levels) to ensure DQ output is in high impedance.

3) Both banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register Set command

in step 4 to stabilize the internal circuitry of the device.

TM Technology Inc. reserves the right

P. 20

to change products or specifications without notice.

Publication Date: FEB. 2007

Revision: A

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