NCP3020A Ver la hoja de datos (PDF) - ON Semiconductor

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componentes Descripción

Fabricante

NCP3020A

Synchronous PWM Controller

ON Semiconductor 

NCP3020A, NCP3020B, NCV3020A, NCV3020B

Reduced sampling time occurs at high duty cycles where

the low side MOSFET is off for the majority of the switching

period. Reduced sampling time causes errors in the

regulated voltage on the boost pin. High duty cycle / input

voltage induced sampling errors can result in increased

boost ripple voltage or higher than desired DC boost voltage.

Figure 29 outlines all operating regions.

The recommended operating conditions are shown in

Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor

can be placed on the boost pin without causing damage to the

device or MOSFETS. Larger boost ripple voltage occurring

over several switching cycles is shown in Region 2 (Yellow).

The boost ripple frequency is dependent on the output

capacitance selected. The ripple voltage will not damage the

device or $12 V gate rated MOSFETs.

Conditions where maximum boost ripple voltage could

damage the device or $12 V gate rated MOSFETs can be

seen in Region 3 (Orange). Placing a boost capacitor that is

no greater than 10X the input capacitance of the high side

MOSFET on the boost pin limits the maximum boost

voltage < 12 V. The typical drive waveforms for Regions 1,

2 and 3 (green, yellow, and orange) regions of Figure 29 are

shown in Figure 30.

Boost Voltage Levels

Normal Operation

28

26

Increased Boost Ripple

(Still in Specification)

Increased Boost Ripple

Capacitor Optimization

Required

Region 3

24

22

22V

20

18

Region 2

Maxi

16

Region 1

Mmauxm

DDuutyty

14

CCyycclele

12

10

11 .5V

8

71%

6

4

2

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Duty Cycle

Figure 29. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor

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