MT9160B Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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componentes Descripción

Fabricante

MT9160B

ISO²-CMOS 5 Volt Multi-Featured Codec (MFC) Advance Information

Zarlink Semiconductor Inc 

MT9160B/61B

Advance Information

Register Summary

Address

00

01

02

03

04

05

06

07y

Bit 7

RxINC

-

-

PDFDI

CEN

C7

D7

-

Bit 6

RxFG2

Bit 5

RxFG1

Bit 4

RxFG0

Bit 3

TxINC

Bit 2

TxFG2

Bit 1

TxFG1

-

-

-

-

STG2 STG1

-

PDDR

-

RST

-

-

-

-

-

TxMute RxMute TxBsel

DEN

D8

C6

C5

A/µ

Smag/ CSL2 CSL1

ITU-T

C4

C3

C2

C1

D6

D5

D4

D3

D2

D1

-

-

-

PCM/ loopen

-

ANALOG

Table 2 - 5V Multi-featured Codec Register Map

Bit 0

TxFG0

STG0

DrGain

RxBsel

CSL0

C0

D0

-

Description

Gain Control

Register 1

Gain Control

Register 2

Path Control

Control

Register 1

Control

Register 2

C-Channel

Register

D-Channel

Register

Loop Back

Gain Control Register 1

ADDRESS = 00h WRITE/READ VERIFY

RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0

7

6

5

4

3

2

1

0

Power Reset Value

1000 0000

Receive Gain

Setting (dB)

(default) 0

-1

-2

-3

-4

-5

-6

-7

RxFG2

0

0

0

0

1

1

1

1

RxFGn = Receive Filter Gain bit n

RxFG1

0

0

1

1

0

0

1

1

RxFG0

0

1

0

1

0

1

0

1

Transmit Gain

Setting (dB)

(default) 0

1

2

3

4

5

6

7

TxFG2

0

0

0

0

1

1

1

1

TxFGn = Transmit Filter Gain bit n

RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.

TxINC: When high, the transmit nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.

TxFG1

0

0

1

1

0

0

1

1

TxFG0

0

1

0

1

0

1

0

1

Note: Bits marked "-" are reserved bits and should be written with logic "0"

89

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