MT9160B Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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MT9160B

ISO²-CMOS 5 Volt Multi-Featured Codec (MFC) Advance Information

Zarlink Semiconductor Inc 

Advance Information

MT9160B/61B

Gain Control Register 2

ADDRESS = 01h WRITE/READ VERIFY

-

-

-

-

- STG2 STG1 STG0

7

6

5

4

3

2

1

0

Power Reset Value

XXXX X000

Side-tone Gain

Setting (dB)

(default) OFF

-9.96

-6.64

-3.32

0

3.32

6.64

9.96

STG2

0

0

0

0

1

1

1

1

STGn = Side-tone Gain bit n

STG1

0

0

1

1

0

0

1

1

STG0

0

1

0

1

0

1

0

1

Path Control

ADDRESS = 02h WRITE/READ VERIFY

-

-

-

-

-

-

- DrGain

7

6

5

4

3

2

1

0

Power Reset Value

XX00 0000

DrGain

When high, the receive path is summed with the side tone path and is attenuated by 6dB.

When low, the receive path contains no side tone (default).

Note: Bits marked "-" are reserved bits and should be written with logic "0"

90

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