EM78P142SS10J Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78P142SS10J Datasheet PDF : 96 Pages
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EM78P142
8-Bit Microprocessor with OTP ROM
6.1.13 RD (ADDATA1L: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2
and Wake-up Control Register).
RD is read only
6.1.14 RE (Interrupt Status 2 and Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
“0”
ADWE
“0”
ICWE LVDWE
Note: 1. RE <6, 5> can be cleared by instruction but cannot be set.
2. IOCE0 is the interrupt mask register.
3. Reading RE will result to “logic AND” of the RE and IOCE0.
Bit 7 (/LVD):
Bit 6 (LVDIF):
Low voltage Detector state. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by
LVD1 and LVD0), this bit will be cleared.
0 = low voltage is detected
1 = low voltage is not detected or LVD function is disabled
Low Voltage Detector interrupt flag
LVDIF is reset to “0” by software.
Bit 5 (ADIF):
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 4:
This bit must be set to “0” all the time.
Bit 3 (ADWE): ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
When AD Conversion enters sleep/idle mode, this bit must be set to “Enable“.
Bit 2:
This bit must be set to “0” all the time.
Bit 1 (ICWE): Port 5 input change to wake-up status enable bit
0 = Disable Port 5 input change to wake-up status
1 = Enable Port 5 input change to wake-up status
When Port 5 change enters sleep/idle mode, this bit must be set to “Enable“.
14 •
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
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