CMX635 Ver la hoja de datos (PDF) - CML Microsystems Plc
Número de pieza
componentes Descripción
Fabricante
CMX635 Datasheet PDF : 97 Pages
| |||
ISDN Subscriber Processor
CMX635
transmitted an interruptable ‘Frame Complete’ flag is raised and after all of the frames have been
transmitted an interruptable ‘All Frames Complete’ flag is raised.
The second method allows for multiple frames of differing lengths to be transmitted. The number
of octets in the following frame is written to the FIFO prepending the frame data. This is repeated
for each frame in the multiple frame. During transmission the Octet Count is read from the FIFO
and used as in method 1 above along with the pre-programmed Frame Count. After each frame
the next Octet Count is loaded from the FIFO until all frames have been transmitted.
A Received Octet Counter is available to facilitate multiple frame reception. When a frame has
been successfully received the software is required to respond to a Good Packet interrupt by
reading and storing the Received Octet counter value. This value can then be used for
reconstructing the received frame when the FIFO is eventually read. As the counter is only
modulo 256, a rollover indication is provided to enable handling of long frames.
1.5.3
The IOM Interface
The CMX635 contains an industry standard IOM-2 interface to facilitate data transfer and
programming of other IOM-2 compliant devices such as the CMX625 ISDN TA POTS Interface. A
summary of the IOM-2 standard may be found in section 1.7.2 of this document.
The interface operates in Terminal Mode where 3 channels of 4 octets are transmitted per frame.
The IOM-2 standard defines octets in each frame for:
• 8 bits of B1 and B2 data and 2 bits of D data.
• 8 bits of Monitor 0 data + 2 handshake bits, used for layer-1 device control functions.
• 8 bits of Monitor 1 data + 2 handshake bits, used for programming and interrogation of
other IOM devices.
• 4 bits of Control/Indicate (CI) 0 data used for passing layer-1 primitives.
• 6 bits of Control/Indicate (CI) 1 data used for real time status indication between IOM
devices.
• 2 8-bit channels of Inter-Communication data (IC0 & IC1) used as alternative 64kb/s
data channels.
• An 8-bit TIC (Terminal IC) bus used for D-channel access from other layer-2 devices.
The IOM interface can be configured as a timing master, where the IOM clock (DCL) and the IOM
frame sync. (FSC) are generated by the device, or as a timing slave where an external device
provides the clock and sync. signals. Typically the CMX635 will be configured as a timing master
when used in a TE system and a timing slave (taking the clock and sync signals from a U
interface transceiver) in an NT system. The CMX635 always operates as a control master device.
The IOM-2 clock in terminal mode is nominally 1.536MHz giving 192 clocks per 8kHz frame, or 2
clocks per data bit. The FSC and DCL are derived from the recovered 192kHz S/T sample clock,
which maintains PCM octet synchronisation. In NT mode, as a timing slave, the incoming FSC is
used to synchronise the generated 192kHz S/T data.
The monitor channels (0 and 1) provide a mechanism for passing programming and information
octets between the master and slave IOM devices. Only 1 channel can be active at a time, the
active channel being selectable from the ‘IOM Monitor Channel Control’ register. The monitor
handshake protocol in the IOM specification is generated automatically within the CMX635 and
any errors in the handshaking or received data will abort the transmit/receive sequence and raise
interruptable abort flags in the ‘IOM Status’ register.
The operation of the B, D and IC channels is fully autonomous and they are activated by routing
data to and from the appropriate channels using the ‘Data Routing’ registers (section 1.5.6).
Data is transmitted in the selected monitor channel by writing to the ‘Monitor Channel Transmit’
register when the Tx channel is idle. The ‘Monitor Tx Buffer Empty’ status flag will indicate when
© 2001 Consumer Microcircuits Limited
17
D/635/2
Share Link: 