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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

The address field matching function can be used in the D-channel to match incoming SAPI and

TEI identifiers automatically. When address matching is turned on, incoming data frames are

ignored unless the required address fields match the pre-programmed values. 4 independent

match addresses can be programmed for each of the 1st and 2nd address fields as well as the

broadcast addresses for both fields. The extent of address matching required can be selected to

be zero, one or both fields. The combination of the pre-programmed match registers to be used is

also programmable. A successful address match will set an interruptible status bit. If address

matching is turned off, all incoming frames are routed to the receive FIFO irrespective of address

values and the software must determine if the frame is relevant.

For transmit frames, either 1 or 2 address registers may be prepended to the transmit FIFO data

automatically unless User Address mode is selected, in which case the address fields must be

written to the FIFO as part of the data frame by software.

The CMX635 can automatically generate and decode the16 bit CRC fields appended to the end of

HDLC frames and for received frames will generate an interruptable Good Packet or CRC Error

status as appropriate. If automatic CRC handling is not required, the transmit CRC value can be

supplied by the user and written as the last data octet(s) to the FIFO. For received frames the

CRC value available as the last octet(s) in the receive FIFO can be decoded in software. If

automatic CRC generation is enabled, a facility is provided to force a CRC error for purposes of

system test/checks.

Status flags are provided to indicate a number of abnormal conditions, which can be configured to

generate interrupt requests. The conditions indicated are:

• Received CRC error

• Received octet mis-alignment (frame not an integer number of octets)

• Received packet aborted (7 consecutive binary 1’s received)

• Received short packet (frame length less that pre-programmed minimum)

• Transmit aborted (collision detected In the D-channel)

The CMX635 contains a FIFO, for each of the B receive and transmit channels and the D receive

and transmit channel (6 total). The FIFOs are implemented as part of a 1024 byte RAM and the

FIFO depths can be independently configured for each channel, in 4 byte increments, up to the

1024 byte RAM size. The sum of FIFO sizes must not exceed the 1024 byte limit. A full set of

FIFO status indicators are available for each channel including ‘Full’, ‘Empty’, ‘Near Full’, ‘Near

Empty’, ‘Over-Write’ and ‘Under-Read’. The ‘Near Full’ and ‘Near Empty’ status indicate when

the FIFO is 8 bytes from being full and 8 bytes from being empty respectively. The ‘Full’ and

‘Empty’ status have programmable polarity to allow for alternative interrupt generation on ‘Not

Full’ and ‘Not Empty’. Each FIFO can be individually cleared which obviates the need to read the

entire FIFO if an error or abort is detected.

When a valid frame is detected the receive FIFOs are always written with all data between

opening and closing flags, irrespective of the address matching and CRC checking selected.

The CMX635 HDLC controllers have extensive functionality to allow transmission and reception

of multiple frames of data without processor intervention, subject to the FIFO depths set. Two

methods are available for multiple frame transmission.

The first method allows multiple frames of the same length to be transmitted by writing an Octet

Count register with the frame length and a Frame Count register with the required number of

frames. The data to be transmitted is then written contiguously to the FIFO. When HDLC

transmission is enabled, the Octet Counter (which can be read asynchronously by software)

defines the FIFO data frame boundaries and decrements as each octet is transmitted. After each

frame the Frame Counter is decremented to a minimum count of 1. After each frame has been

© 2001 Consumer Microcircuits Limited

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D/635/2

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