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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

The Frame Synchronisation function detects the correct occurrence of Framing and Auxiliary

Framing pulses and in TE mode adjusts the receive and transmit frames accordingly. Two

consecutive correctly received frames are required before the interface is designated as Frame

Locked.

D-channel access in TE mode is initiated by writing the ‘Data Request’ primitive to the CMX635

along with the required primary priority level. The primary priority can be set to 8 for signalling

frames and to 10 for data frames. The D-channel Access function will then ensure that the D-

channel is available by monitoring the number of consecutive D-channel Echo bits that are set to

binary 1. If the count reaches the level defined by the priority, the D-channel HDLC block is

allowed to transmit. If an echo bit is received that does not match the transmitted D bit, the D-

channel is released and a ‘Collision’ status flag is set. A ‘Data Indication’ primitive can be

configured to generate an interrupt when the D-channel has been successfully acquired. After

transmission of an HDLC frame, and if another frame is pending, the priority is automatically

decreased (8 to 9 and 10 to 11) to allow other TE devices access to the D-channel. If multiple D-

channel transmission frames are set up in the HDLC FIFO (see section 1.5.2) the access

mechanism will automatically allow other TE’s access to the D-channel between frames but will

remain active until all frames are sent.

D-channel access in intelligent NT mode uses a similar access mechanism to TE mode but the D

bits from the downstream TE’s are used to determine D-channel activity instead of the echo bits.

When an NT has successfully acquired the D-channel it sets the echo bits to the downstream TE’s

to binary 0, thus inhibiting TE D-channel access.

The CMX635 supports full ST Multi-framing capability and in TE mode will synchronise to

incoming multi-frame markers. In NT mode formatted multi-frames are generated. The CMX635

is capable of processing 1 ‘Q’ channel and ‘5’ S channels as defined in ITU-T I.430. Full sets of

interruptible status flags are available to indicate when the transmit/receive data buffers require

servicing.

1.5.2 The HDLC Controllers and FIFOs

The CMX635 contains flexible Controllers and FIFOs for both B-channels and the D-channel that

can be individually selected and enabled.

The main functions of the HDLC Controllers and FIFOs are:

• Flag generation/recognition

• Bit Stuffing/Destuffing and Octet Alignment

• Address Field Matching

• CRC generation/checking

• Re-configurable FIFO data buffers on all transmit and receive channels

• Multiple HDLC frame generation and Reception

The CMX635 will automatically generate the 01111110b sequence defined as an HDLC flag at

the beginning of each new frame. Reception of an HDLC frame will initiate the frame receive

sequence and the reception of a second flag will be interpreted as the end of an HDLC frame.

‘Shared’ flags (1 flag between the end of a frame and the start of a new frame) will be processed

correctly in the receive channel. In the B transmit channels a ‘shared’ flag can optionally be used

between multiple frames.

The bit stuffing and de-stuffing requirements of the HDLC protocol are automatically implemented

unless the fully transparent modes of operation are selected. If transparent receive mode for a B-

channel is selected, the serial bit stream is formed directly into octets and written to the receive

FIFO. Transparent receive mode is not available in the D-channel. If transparent transmit mode is

selected, the data from the FIFO is read in octets and transmitted directly as a serial bit stream

octet aligned with the ST frame B-channel octets.

© 2001 Consumer Microcircuits Limited

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D/635/2

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