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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

The CMX635 is highly configurable, via internal software accessible registers, to operate in a wide

variety of applications. The details of every configuration and Status Register are described in the

Programming Guide section 1.6.

The main functions of the CMX635 are shown in the block diagrams and are conceptually:

• The ST interface and Digital Phase Locked Loop

• The HDLC Controllers and FIFOs

• The IOM Interface

• The G.711 Codec and Analogue Gain Path

• The Tone Generator and Tone Decoder

• The Channel Routing Block

• Speaker Phone Functions

• The Processor Interface, Top Level Status and Power Control

1.5.1 The ST interface and Digital Phase Locked Loop

The ST Interface performs the following functions:

• S/T Bus Activation/Deactivation Control

• Clock and Data Recovery

• Frame Synchronisation

• D-channel Access

• Multi-Frame Generation/Reception

The Activation/Deactivation control when configured in TE mode follows closely the ITU-T I.430

requirements and is mainly autonomous (Timer T3 requiring implementation in software). The

activation states are advanced through automatic detection of the INFO0, INFO2 and INFO4

signals on the receive bus and are initiated by software writes of the Activate and Deactivate

request primitives and the Power Up/Down status. Note that although the ITU specification

provides no facility for the ST bus to be deactivated directly by the TE, the Deactivate Request

control is provided to allow implementation of timer T3 in software. The ST activation state can

be read by software and the detection of the various INFO signals can be configured to generate

an interrupt if required. The activation status indicators ‘Connect Indication’, ‘Activate Indication’

and ‘Error Indication’ are available to the software and may also be configured to generate an

interrupt request if required.

The ST interface autonomously outputs the ‘INFO0’, ‘INFO1’ and ‘INFO3’ signals at the

appropriate states of activation/deactivation.

For NT mode of operation, the next state is under software control and is written directly to the ST

interface. The detection of ‘INFO0’, ‘INFO1’ and ‘INFO3’ is available to the software to enable

next state calculation.

The Data Recovery function consists of an analogue section and a digital section. The analogue

ST receiver continuously tracks the amplitude of the incoming signal and uses an adaptive slicing

level to recover digital data from the 3 level receiver input. The data is coded into positive pulse,

negative pulse or no pulse. The digital section over-samples the recovered data and performs a

majority decision algorithm to determine the correct recovered bit stream.

The Clock Recovery function consists of a digital phase-locked loop that tracks the raw sampled

data in TE mode to produce a filtered and frequency locked master sample clock at a nominal

192kHz. This clock is used to sample the recovered receive bit stream and to generate a phase

locked ST transmit clock. In NT mode the ST bit clock tracks the received IOM FSC signal thus

maintaining network synchronisation.

© 2001 Consumer Microcircuits Limited

14

D/635/2

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